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Rpi 4.4.y spi aux #1295

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a46b4d7
clk: bcm2835: Add bindings for the auxiliary peripheral clock gates.
anholt Dec 15, 2015
3c17ef3
clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.
anholt Dec 15, 2015
736ed8a
SPI auxiliaries (SPI1 & SPi2)
frasersdev Feb 20, 2016
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31 changes: 31 additions & 0 deletions Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt
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@@ -0,0 +1,31 @@
Broadcom BCM2835 auxiliary peripheral support

This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt

The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
area controlling clock gating to the peripherals, and providing an IRQ
status register.

Required properties:
- compatible: Should be "brcm,bcm2835-aux"
- #clock-cells: Should be <1>. The permitted clock-specifier values can be
found in include/dt-bindings/clock/bcm2835-aux.h
- reg: Specifies base physical address and size of the registers
- clocks: The parent clock phandle

Example:

clocks: cprman@7e101000 {
compatible = "brcm,bcm2835-cprman";
#clock-cells = <1>;
reg = <0x7e101000 0x2000>;
clocks = <&clk_osc>;
};

aux: aux@0x7e215004 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
reg = <0x7e215000 0x8>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
};
41 changes: 41 additions & 0 deletions arch/arm/boot/dts/bcm2708-rpi-b-plus.dts
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Expand Up @@ -22,6 +22,16 @@
brcm,pins = <8 7>;
brcm,function = <1>; /* output */
};

spi1_pins: spi1_pins {
brcm,pins = <19 20 21>;
brcm,function = <3>; /* alt4 */
};

spi1_cs_pins: spi1_cs_pins {
brcm,pins = <18 17 16>;
brcm,function = <1>; /* output */
};

i2c0_pins: i2c0 {
brcm,pins = <0 1>;
Expand Down Expand Up @@ -76,6 +86,36 @@
};
};

&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
cs-gpios = <&gpio 18 1>, <&gpio 17 1>, <&gpio 16 1>;

spidev@0{
compatible = "spidev";
reg = <0>; /* CE0 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};

spidev@1{
compatible = "spidev";
reg = <1>; /* CE1 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};

spidev@2{
compatible = "spidev";
reg = <2>; /* CE2 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};
};

&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
Expand Down Expand Up @@ -122,6 +162,7 @@
uart0_clkrate = <&clk_uart0>,"clock-frequency:0";
i2s = <&i2s>,"status";
spi = <&spi0>,"status";
spi1_aux = <&spi1>,"status";
i2c0 = <&i2c0>,"status";
i2c1 = <&i2c1>,"status";
i2c2_iknowwhatimdoing = <&i2c2>,"status";
Expand Down
83 changes: 83 additions & 0 deletions arch/arm/boot/dts/bcm2708-rpi-cm.dts
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Expand Up @@ -20,6 +20,27 @@
brcm,pins = <8 7>;
brcm,function = <1>; /* output */
};


spi1_pins: spi1_pins {
brcm,pins = <19 20 21>;
brcm,function = <3>; /* alt4 */
};

spi1_cs_pins: spi1_cs_pins {
brcm,pins = <18 17 16>;
brcm,function = <1>; /* output */
};

spi2_pins: spi2_pins {
brcm,pins = <40 41 42>;
brcm,function = <3>; /* alt4 */
};

spi2_cs_pins: spi2_cs_pins {
brcm,pins = <45 44 43>;
brcm,function = <1>; /* output */
};

i2c0_pins: i2c0 {
brcm,pins = <0 1>;
Expand Down Expand Up @@ -59,6 +80,66 @@
};
};

&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
cs-gpios = <&gpio 18 1>, <&gpio 17 1>, <&gpio 16 1>;

spidev@0{
compatible = "spidev";
reg = <0>; /* CE0 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};

spidev@1{
compatible = "spidev";
reg = <1>; /* CE1 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};

spidev@2{
compatible = "spidev";
reg = <2>; /* CE2 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};
};

&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins &spi2_cs_pins>;
cs-gpios = <&gpio 45 1>, <&gpio 44 1>, <&gpio 43 1>;

spidev@0{
compatible = "spidev";
reg = <0>; /* CE0 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};

spidev@1{
compatible = "spidev";
reg = <1>; /* CE1 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};

spidev@2{
compatible = "spidev";
reg = <2>; /* CE2 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};
};

&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
Expand Down Expand Up @@ -91,6 +172,8 @@
uart0_clkrate = <&clk_uart0>,"clock-frequency:0";
i2s = <&i2s>,"status";
spi = <&spi0>,"status";
spi1_aux = <&spi1>,"status";
spi2_aux = <&spi2>,"status";
i2c0 = <&i2c0>,"status";
i2c1 = <&i2c1>,"status";
i2c2_iknowwhatimdoing = <&i2c2>,"status";
Expand Down
36 changes: 34 additions & 2 deletions arch/arm/boot/dts/bcm2708_common.dtsi
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@@ -1,3 +1,4 @@
#include <dt-bindings/clock/bcm2835-aux.h>
#include "skeleton.dtsi"

/ {
Expand All @@ -19,6 +20,8 @@
spi0 = &spi0;
i2c0 = &i2c0;
uart1 = &uart1;
spi1 = &spi1;
spi2 = &spi2;
mmc = &mmc;
i2c1 = &i2c1;
i2c2 = &i2c2;
Expand Down Expand Up @@ -185,6 +188,13 @@
#pwm-cells = <2>;
status = "disabled";
};

aux: aux@0x7e215004 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
reg = <0x7e215000 0x8>;
clocks = <&clk_core>;
};

uart1: uart@7e215040 {
compatible = "brcm,bcm2835-aux-uart", "ns16550";
Expand All @@ -194,8 +204,30 @@
reg-shift = <2>;
no-loopback-test;
status = "disabled";
};

};

spi1: spi@7e215080 {
compatible = "brcm,bcm2835-aux-spi";
reg = <0x7e215080 0x40>, <0x7e215000 0x8>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cs-gpios = <0>, <0>, <0>;
};

spi2: spi@7e2150C0 {
compatible = "brcm,bcm2835-aux-spi";
reg = <0x7e2150C0 0x40>, <0x7e215000 0x8>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cs-gpios = <0>, <0>, <0>;
};

mmc: mmc@7e300000 {
compatible = "brcm,bcm2835-mmc";
reg = <0x7e300000 0x100>;
Expand Down
41 changes: 41 additions & 0 deletions arch/arm/boot/dts/bcm2709-rpi-2-b.dts
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Expand Up @@ -22,6 +22,16 @@
brcm,pins = <8 7>;
brcm,function = <1>; /* output */
};

spi1_pins: spi1_pins {
brcm,pins = <19 20 21>;
brcm,function = <3>; /* alt4 */
};

spi1_cs_pins: spi1_cs_pins {
brcm,pins = <18 17 16>;
brcm,function = <1>; /* output */
};

i2c0_pins: i2c0 {
brcm,pins = <0 1>;
Expand Down Expand Up @@ -76,6 +86,36 @@
};
};

&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
cs-gpios = <&gpio 18 1>, <&gpio 17 1>, <&gpio 16 1>;

spidev@0{
compatible = "spidev";
reg = <0>; /* CE0 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};

spidev@1{
compatible = "spidev";
reg = <1>; /* CE1 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};

spidev@2{
compatible = "spidev";
reg = <2>; /* CE2 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <500000>;
};
};

&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
Expand Down Expand Up @@ -122,6 +162,7 @@
uart0_clkrate = <&clk_uart0>,"clock-frequency:0";
i2s = <&i2s>,"status";
spi = <&spi0>,"status";
spi1_aux = <&spi1>,"status";
i2c0 = <&i2c0>,"status";
i2c1 = <&i2c1>,"status";
i2c2_iknowwhatimdoing = <&i2c2>,"status";
Expand Down
1 change: 1 addition & 0 deletions arch/arm/configs/bcm2709_defconfig
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Expand Up @@ -598,6 +598,7 @@ CONFIG_I2C_BCM2708=m
CONFIG_I2C_GPIO=m
CONFIG_SPI=y
CONFIG_SPI_BCM2835=m
CONFIG_SPI_BCM2835AUX=m
CONFIG_SPI_SPIDEV=y
CONFIG_PPS=m
CONFIG_PPS_CLIENT_LDISC=m
Expand Down
1 change: 1 addition & 0 deletions arch/arm/configs/bcmrpi_defconfig
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Expand Up @@ -591,6 +591,7 @@ CONFIG_I2C_BCM2708=m
CONFIG_I2C_GPIO=m
CONFIG_SPI=y
CONFIG_SPI_BCM2835=m
CONFIG_SPI_BCM2835AUX=m
CONFIG_SPI_SPIDEV=y
CONFIG_PPS=m
CONFIG_PPS_CLIENT_LDISC=m
Expand Down
1 change: 1 addition & 0 deletions drivers/clk/bcm/Makefile
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Expand Up @@ -4,6 +4,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
obj-$(CONFIG_ARCH_BCM2835)$(CONFIG_ARCH_BCM2708)$(CONFIG_ARCH_BCM2709) += clk-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835)$(CONFIG_ARCH_BCM2708)$(CONFIG_ARCH_BCM2709) += clk-bcm2835-aux.o
obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o
obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o
Expand Down
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