Rpi 4.4.y SPI auxiliaries with overlays

Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt

@@ -0,0 +1,31 @@
+Broadcom BCM2835 auxiliary peripheral support
+
+This binding uses the common clock binding:
+    Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
+area controlling clock gating to the peripherals, and providing an IRQ
+status register.
+
+Required properties:
+- compatible:	Should be "brcm,bcm2835-aux"
+- #clock-cells:	Should be <1>. The permitted clock-specifier values can be
+		  found in include/dt-bindings/clock/bcm2835-aux.h
+- reg:		Specifies base physical address and size of the registers
+- clocks:	The parent clock phandle
+
+Example:
+
+	clocks: cprman@7e101000 {
+		compatible = "brcm,bcm2835-cprman";
+		#clock-cells = <1>;
+		reg = <0x7e101000 0x2000>;
+		clocks = <&clk_osc>;
+	};
+
+	aux: aux@0x7e215004 {
+		compatible = "brcm,bcm2835-aux";
+		#clock-cells = <1>;
+		reg = <0x7e215000 0x8>;
+		clocks = <&clocks BCM2835_CLOCK_VPU>;
+	};

arch/arm/boot/dts/bcm2708_common.dtsi

@@ -1,10 +1,12 @@
+#include <dt-bindings/clock/bcm2835-aux.h>
 #include "skeleton.dtsi"
 
 / {
 	interrupt-parent = <&intc>;
 
 	aliases {
 		audio = &audio;
+		aux = &aux;
 		sound = &sound;
 		soc = &soc;
 		dma = &dma;
@@ -19,6 +21,8 @@
 		spi0 = &spi0;
 		i2c0 = &i2c0;
 		uart1 = &uart1;
+		spi1 = &spi1;
+		spi2 = &spi2;
 		mmc = &mmc;
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
@@ -186,6 +190,14 @@
 			status = "disabled";
 		};
 
+		aux: aux@0x7e215004 {
+			compatible = "brcm,bcm2835-aux";
+			#clock-cells = <1>;
+			reg = <0x7e215000 0x8>;
+			clocks = <&clk_core>;
+			status = "disabled";
+		};
+
 		uart1: uart@7e215040 {
 			compatible = "brcm,bcm2835-aux-uart", "ns16550";
 			reg = <0x7e215040 0x40>;
@@ -194,7 +206,27 @@
 			reg-shift = <2>;
 			no-loopback-test;
 			status = "disabled";
-	        };
+		};
+
+		spi1: spi@7e215080 {
+			compatible = "brcm,bcm2835-aux-spi";
+			reg = <0x7e215080 0x40>, <0x7e215000 0x8>;
+			interrupts = <1 29>;
+			clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
+			#address-cells = <1>;
+			#size-cells = <0>;			
+			status = "disabled";
+		};	
+
+		spi2: spi@7e2150C0 {
+			compatible = "brcm,bcm2835-aux-spi";
+			reg = <0x7e2150C0 0x40>, <0x7e215000 0x8>;
+			interrupts = <1 29>;
+			clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
+			#address-cells = <1>;
+			#size-cells = <0>;			
+			status = "disabled";
+		};		
 
 		mmc: mmc@7e300000 {
 			compatible = "brcm,bcm2835-mmc";

arch/arm/boot/dts/overlays/Makefile

@@ -57,6 +57,12 @@ dtb-$(RPI_DT_OVERLAYS) += sdtweak-overlay.dtb
 dtb-$(RPI_DT_OVERLAYS) += smi-dev-overlay.dtb
 dtb-$(RPI_DT_OVERLAYS) += smi-nand-overlay.dtb
 dtb-$(RPI_DT_OVERLAYS) += smi-overlay.dtb
+dtb-$(RPI_DT_OVERLAYS) += spi1-1cs-overlay.dtb
+dtb-$(RPI_DT_OVERLAYS) += spi1-2cs-overlay.dtb
+dtb-$(RPI_DT_OVERLAYS) += spi1-3cs-overlay.dtb
+dtb-$(RPI_DT_OVERLAYS) += spi2-1cs-overlay.dtb
+dtb-$(RPI_DT_OVERLAYS) += spi2-2cs-overlay.dtb
+dtb-$(RPI_DT_OVERLAYS) += spi2-3cs-overlay.dtb
 dtb-$(RPI_DT_OVERLAYS) += spi-gpio35-39-overlay.dtb
 dtb-$(RPI_DT_OVERLAYS) += tinylcd35-overlay.dtb
 dtb-$(RPI_DT_OVERLAYS) += uart1-overlay.dtb

arch/arm/boot/dts/overlays/README

@@ -707,6 +707,105 @@ Load:   dtoverlay=smi-nand
 Params: <None>
 
 
+Name:   spi1-1cs
+Info:   Enables spi1 with a single chip select (CS) line and associated spidev 
+        dev node. The gpio pin number for the CS line and spidev device node 
+        creation are configurable.
+        N.B.: spi1 is only accessible on devices with a 40pin header, eg:
+              A+, B+, Zero and PI2 B; as well as the Compute Module.
+Load:   dtoverlay=spi1-1cs,<param>=<val>
+Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI1_CE0).
+        cs0_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev1.0 (default 
+                                is 'okay' or enabled).
+
+
+Name:   spi1-2cs
+Info:   Enables spi1 with a two chip select (CS) lines and associated spidev 
+        dev nodes. The gpio pin numbers for the CS lines and spidev device node 
+        creation are configurable.
+        N.B.: spi1 is only accessible on devices with a 40pin header, eg:
+              A+, B+, Zero and PI2 B; as well as the Compute Module.
+Load:   dtoverlay=spi1-2cs,<param>=<val>
+Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI1_CE0).
+        cs1_pin                 GPIO pin for CS1 (default 17 - BCM SPI1_CE1).
+        cs0_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev1.0 (default 
+                                is 'okay' or enabled).
+        cs1_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev1.1 (default 
+                                is 'okay' or enabled).                               
+
+
+Name:   spi1-3cs
+Info:   Enables spi1 with a three chip select (CS) lines and associated spidev 
+        dev nodes. The gpio pin numbers for the CS lines and spidev device node 
+        creation are configurable.
+        N.B.: spi1 is only accessible on devices with a 40pin header, eg:
+              A+, B+, Zero and PI2 B; as well as the Compute Module.
+Load:   dtoverlay=spi1-3cs,<param>=<val>
+Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI1_CE0).
+        cs1_pin                 GPIO pin for CS1 (default 17 - BCM SPI1_CE1).
+        cs2_pin                 GPIO pin for CS2 (default 16 - BCM SPI1_CE2).
+        cs0_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev1.0 (default 
+                                is 'okay' or enabled).
+        cs1_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev1.1 (default 
+                                is 'okay' or enabled).  
+        cs2_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev1.2 (default 
+                                is 'okay' or enabled).  
+
+
+Name:   spi2-1cs
+Info:   Enables spi2 with a single chip select (CS) line and associated spidev 
+        dev node. The gpio pin number for the CS line and spidev device node 
+        creation are configurable.
+        N.B.: spi2 is only accessible with the Compute Module.
+Load:   dtoverlay=spi2-1cs,<param>=<val>
+Params: cs0_pin                 GPIO pin for CS0 (default 43 - BCM SPI2_CE0).
+        cs0_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev2.0 (default 
+                                is 'okay' or enabled).
+
+
+Name:   spi2-2cs
+Info:   Enables spi2 with a two chip select (CS) lines and associated spidev 
+        dev nodes. The gpio pin numbers for the CS lines and spidev device node 
+        creation are configurable.
+        N.B.: spi2 is only accessible with the Compute Module.
+Load:   dtoverlay=spi2-2cs,<param>=<val>
+Params: cs0_pin                 GPIO pin for CS0 (default 43 - BCM SPI2_CE0).
+        cs1_pin                 GPIO pin for CS1 (default 44 - BCM SPI2_CE1).
+        cs0_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev2.0 (default 
+                                is 'okay' or enabled).
+        cs1_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev2.1 (default 
+                                is 'okay' or enabled).                                
+
+
+Name:   spi2-3cs
+Info:   Enables spi2 with a three chip select (CS) lines and associated spidev 
+        dev nodes. The gpio pin numbers for the CS lines and spidev device node 
+        creation are configurable.
+        N.B.: spi2 is only accessible with the Compute Module.
+Load:   dtoverlay=spi2-3cs,<param>=<val>
+Params: cs0_pin                 GPIO pin for CS0 (default 43 - BCM SPI2_CE0).
+        cs1_pin                 GPIO pin for CS1 (default 44 - BCM SPI2_CE1).
+        cs2_pin                 GPIO pin for CS2 (default 45 - BCM SPI2_CE2).
+        cs0_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev2.0 (default 
+                                is 'okay' or enabled).
+        cs1_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev2.1 (default 
+                                is 'okay' or enabled). 
+        cs2_spidev              Set to 'disabled' to stop the creation of a 
+                                userspace device node /dev/spidev2.2 (default 
+                                is 'okay' or enabled). 
+
+
 Name:   spi-gpio35-39
 Info:   move SPI function block to GPIO 35 to 39
 Load:   dtoverlay=spi-gpio35-39

arch/arm/boot/dts/overlays/spi1-1cs-overlay.dts

@@ -0,0 +1,57 @@
+/dts-v1/;
+/plugin/;
+
+
+/ {
+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
+
+	fragment@0 {
+		target = <&gpio>;
+		__overlay__ {
+			spi1_pins: spi1_pins {
+				brcm,pins = <19 20 21>;
+				brcm,function = <3>; /* alt4 */
+			};
+
+			spi1_cs_pins: spi1_cs_pins {
+				brcm,pins = <18>;
+				brcm,function = <1>; /* output */
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&spi1>;
+		frag1: __overlay__ {
+			/* needed to avoid dtc warning */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
+			cs-gpios = <&gpio 18 1>;
+			status = "okay";
+
+			spidev1_0: spidev@0 {
+				compatible = "spidev";
+				reg = <0>;      /* CE0 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				spi-max-frequency = <500000>;
+				status = "okay";
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&aux>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	__overrides__ {
+		cs0_pin  = <&spi1_cs_pins>,"brcm,pins:0",
+			   <&frag1>,"cs-gpios:4";
+		cs0_spidev = <&spidev1_0>,"status";		
+	};
+};

arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts

@@ -0,0 +1,69 @@
+/dts-v1/;
+/plugin/;
+
+
+/ {
+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
+
+	fragment@0 {
+		target = <&gpio>;
+		__overlay__ {
+			spi1_pins: spi1_pins {
+				brcm,pins = <19 20 21>;
+				brcm,function = <3>; /* alt4 */
+			};
+
+			spi1_cs_pins: spi1_cs_pins {
+				brcm,pins = <18 17>;
+				brcm,function = <1>; /* output */
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&spi1>;
+		frag1: __overlay__ {
+			/* needed to avoid dtc warning */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
+			cs-gpios = <&gpio 18 1>, <&gpio 17 1>;
+			status = "okay";
+
+			spidev1_0: spidev@0 {
+				compatible = "spidev";
+				reg = <0>;      /* CE0 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				spi-max-frequency = <500000>;
+				status = "okay";
+			};
+
+			spidev1_1: spidev@1 {
+				compatible = "spidev";
+				reg = <1>;      /* CE1 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				spi-max-frequency = <500000>;
+				status = "okay";
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&aux>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	__overrides__ {
+		cs0_pin  = <&spi1_cs_pins>,"brcm,pins:0",
+			   <&frag1>,"cs-gpios:4";
+		cs1_pin  = <&spi1_cs_pins>,"brcm,pins:4",
+			   <&frag1>,"cs-gpios:16";
+		cs0_spidev = <&spidev1_0>,"status";
+		cs1_spidev = <&spidev1_1>,"status";	
+	};
+};