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Merged
merged 2 commits into from
Jan 17, 2024
Merged

Async updates backport to 6.1 #5861

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7149902
drm/vc4: Add 2712 support to vc4_plane_async_set_fb
6by9 Jan 4, 2024
969c5d8
drm/vc4: Fix atomic_async_check to call the right mode_set function
6by9 Jan 17, 2024
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52 changes: 38 additions & 14 deletions drivers/gpu/drm/vc4/vc4_plane.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1865,7 +1865,7 @@ static int vc6_plane_mode_set(struct drm_plane *plane,
* The UPM buffer will be allocated in
* vc6_plane_allocate_upm().
*/
VC4_SET_FIELD(upper_32_bits(paddr) & 0xf,
VC4_SET_FIELD(upper_32_bits(paddr) & 0xff,
SCALER6_PTR0_UPPER_ADDR));

/* Pointer Word 1 */
Expand Down Expand Up @@ -2068,7 +2068,8 @@ void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
{
struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
struct drm_gem_dma_object *bo = drm_fb_dma_get_gem_obj(fb, 0);
uint32_t addr;
struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
dma_addr_t dma_addr = bo->dma_addr + fb->offsets[0];
int idx;

if (!drm_dev_enter(plane->dev, &idx))
Expand All @@ -2078,19 +2079,38 @@ void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
* because this is only called on the primary plane.
*/
WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
addr = bo->dma_addr + fb->offsets[0];

/* Write the new address into the hardware immediately. The
* scanout will start from this address as soon as the FIFO
* needs to refill with pixels.
*/
writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
if (vc4->gen == VC4_GEN_6) {
u32 value;

/* Also update the CPU-side dlist copy, so that any later
* atomic updates that don't do a new modeset on our plane
* also use our updated address.
*/
vc4_state->dlist[vc4_state->ptr0_offset[0]] = addr;
value = vc4_state->dlist[vc4_state->ptr0_offset[0]] &
~SCALER6_PTR0_UPPER_ADDR_MASK;
value |= VC4_SET_FIELD(upper_32_bits(dma_addr) & 0xff,
SCALER6_PTR0_UPPER_ADDR);

writel(value, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
vc4_state->dlist[vc4_state->ptr0_offset[0]] = value;

value = lower_32_bits(dma_addr);
writel(value, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0] + 1]);
vc4_state->dlist[vc4_state->ptr0_offset[0] + 1] = value;
} else {
u32 addr;

addr = (u32)dma_addr;

/* Write the new address into the hardware immediately. The
* scanout will start from this address as soon as the FIFO
* needs to refill with pixels.
*/
writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);

/* Also update the CPU-side dlist copy, so that any later
* atomic updates that don't do a new modeset on our plane
* also use our updated address.
*/
vc4_state->dlist[vc4_state->ptr0_offset[0]] = addr;
}

drm_dev_exit(idx);
}
Expand Down Expand Up @@ -2174,11 +2194,15 @@ static int vc4_plane_atomic_async_check(struct drm_plane *plane,
{
struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
plane);
struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
struct vc4_plane_state *old_vc4_state, *new_vc4_state;
int ret;
u32 i;

ret = vc4_plane_mode_set(plane, new_plane_state);
if (vc4->gen >= VC4_GEN_6)
ret = vc6_plane_mode_set(plane, new_plane_state);
else
ret = vc4_plane_mode_set(plane, new_plane_state);
if (ret)
return ret;

Expand Down