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RISC-V
The Open-Standard Instruction Set Architecture
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- Zurich, CH
- https://riscv.org
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- riscv-zabha Public
The Zabha extension provides support for byte and halfword atomic memory operations.
riscv/riscv-zabha’s past year of commit activity - riscv-docs-base-container-image Public
A base container image populated with the dependencies to build the RISC-V Documentation.
riscv/riscv-docs-base-container-image’s past year of commit activity - riscv-cfi Public
This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual
riscv/riscv-cfi’s past year of commit activity - riscv-cheri Public
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
riscv/riscv-cheri’s past year of commit activity - riscv-glossary Public
riscv/riscv-glossary’s past year of commit activity - sig-functional-safety-whitepaper Public
GitHub repository for the Functional Safety SIG Whitepaper Development
riscv/sig-functional-safety-whitepaper’s past year of commit activity
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