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Merged
merged 5 commits into from
Oct 3, 2018
Merged

Add SysTick flags #116

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19d3534
Added Pending SV (Service Call) and SysTick flags
qwerty19106 Sep 24, 2018
454bb4e
Fix duplicate PendSV.
qwerty19106 Sep 24, 2018
d9ad9d4
Fix function names and remove exclusive access
qwerty19106 Oct 1, 2018
fac7e85
Remove blank line
qwerty19106 Oct 1, 2018
2cb6f4b
Autoformat scb.rs by rustfmt
qwerty19106 Oct 1, 2018
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48 changes: 38 additions & 10 deletions src/peripheral/scb.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -7,9 +7,9 @@ use volatile_register::RW;
#[cfg(not(armv6m))]
use super::cpuid::CsselrCacheType;
#[cfg(not(armv6m))]
use super::CPUID;
#[cfg(not(armv6m))]
use super::CBP;
#[cfg(not(armv6m))]
use super::CPUID;
use super::SCB;

/// Register block
Expand Down Expand Up @@ -604,13 +604,18 @@ impl SCB {
/// Initiate a system reset request to reset the MCU
pub fn system_reset(&mut self) -> ! {
::asm::dsb();
unsafe { self.aircr.modify(|r|
SCB_AIRCR_VECTKEY | // otherwise the write is ignored
unsafe {
self.aircr.modify(
|r| {
SCB_AIRCR_VECTKEY | // otherwise the write is ignored
r & SCB_AIRCR_PRIGROUP_MASK | // keep priority group unchanged
SCB_AIRCR_SYSRESETREQ // set the bit
) };
SCB_AIRCR_SYSRESETREQ
}, // set the bit
)
};
::asm::dsb();
loop { // wait for the reset
loop {
// wait for the reset
::asm::nop(); // avoid rust-lang/rust#28728
}
}
Expand All @@ -619,6 +624,9 @@ impl SCB {
const SCB_ICSR_PENDSVSET: u32 = 1 << 28;
const SCB_ICSR_PENDSVCLR: u32 = 1 << 27;

const SCB_ICSR_PENDSTSET: u32 = 1 << 26;
const SCB_ICSR_PENDSTCLR: u32 = 1 << 25;

impl SCB {
/// Set the PENDSVSET bit in the ICSR register which will pend the PendSV interrupt
pub fn set_pendsv() {
Expand All @@ -629,9 +637,7 @@ impl SCB {

/// Check if PENDSVSET bit in the ICSR register is set meaning PendSV interrupt is pending
pub fn is_pendsv_pending() -> bool {
unsafe {
(*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET == SCB_ICSR_PENDSVSET
}
unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET == SCB_ICSR_PENDSVSET }
}

/// Set the PENDSVCLR bit in the ICSR register which will clear a pending PendSV interrupt
Expand All @@ -640,4 +646,26 @@ impl SCB {
(*Self::ptr()).icsr.write(SCB_ICSR_PENDSVCLR);
}
}

/// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
#[inline]
pub fn set_pendst() {
unsafe {
(*Self::ptr()).icsr.write(SCB_ICSR_PENDSTSET);
}
}

/// Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending
#[inline]
pub fn is_pendst_pending() -> bool {
unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET }
}

/// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
#[inline]
pub fn clear_pendst() {
unsafe {
(*Self::ptr()).icsr.write(SCB_ICSR_PENDSTCLR);
}
}
}