Add barrier instructions DMB, DSB, ISB

src/asm.rs

@@ -58,3 +58,53 @@ pub fn wfi() {
         () => {}
     }
 }
+
+/// Instruction Synchronization Barrier
+///
+/// Flushes the pipeline in the processor, so that all instructions following the `ISB` are fetched
+/// from cache or memory, after the instruction has been completed.
+pub fn isb() {
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => unsafe {
+            asm!("isb 0xF" : : : "memory" : "volatile");
+        },
+        #[cfg(not(target_arch = "arm"))]
+        () => {}
+    }
+}
+
+/// Data Synchronization Barrier
+///
+/// Acts as a special kind of memory barrier. No instruction in program order after this
+/// instruction can execute until this instruction completes. This instruction completes only when
+/// both:
+///
+///  * any explicit memory access made before this instruction is complete
+///  * all cache and branch predictor maintenance operations before this instruction complete
+pub fn dsb() {
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => unsafe {
+            asm!("dsb 0xF" : : : "memory" : "volatile");
+        },
+        #[cfg(not(target_arch = "arm"))]
+        () => {}
+    }
+}
+
+/// Data Memory Barrier
+///
+/// Ensures that all explicit memory accesses that appear in program order before the `DMB`
+/// instruction are observed before any explicit memory accesses that appear in program order
+/// after the `DMB` instruction.
+pub fn dmb() {
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => unsafe {
+            asm!("dmb 0xF" : : : "memory" : "volatile");
+        },
+        #[cfg(not(target_arch = "arm"))]
+        () => {}
+    }
+}