riscv-peripheral rework
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This PR is being prevented from merging because it presents one of the blocking labels: work in progress, do not merge. |
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This PR is being prevented from merging because it presents one of the blocking labels: work in progress, do not merge. |
romancardenas
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rmsyn
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So far, these changes look really good. Having these common peripherals match with the svd2rust generated code is a great idea.
Implementing a lot of the functionality as traits is also really nice, since it allows providing platform-specific quirks as extension traits.
Feel free to ping when you want a more in-depth review.
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Instead of using associated functions, this PR proposes using methods. The benefits of this change are:
svd2rust. Thus, the PACs using this tool will benefit from a more uniform API.Dereftrait to simplify theperipheral_codegen!macros.I also removed the
embedded-hal-asyncpartial support. The reason for removing this is that while implementing a few asynchronous functions, I noticed that it is difficult to provide a generic and optimized implementation for any RISC-V target. Instead, I think it is more reasonable to implement a customchip-hal-asynccrate that makes the most of the characteristics of a given chip.This is still a work-in-progress PR. I want to make sure that everything works as expected by updating
svd2rustande310x.