Join the bits muching into a single line to improve dev builds #344
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r? @ryankurte (rust_highfive has picked a reviewer for you, use r? to override) |
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Interesting solution. |
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I'm happy to report that this change makes it possible for the first time to build one of my examples (for a STM32F042) in dev mode: 😅 |
burrbull
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Jul 28, 2019
| self.w | ||
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} else if f.width == rsize {
...
self.w.bits = value
self.w
} else {for 0xffff_ffff etc.
rsize you can pass with fields() instead of rty
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I know. 😅Small steps please so our fellow reviewers/approvers can follow what's going on.
adamgreig
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Jul 28, 2019
Also this rectifies many of the tons of https://rust-lang.github.io/rust-clippy/master/index.html#identity_op lints we're getting. Signed-off-by: Daniel Egger <[email protected]>
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344: Join the bits muching into a single line to improve dev builds r=adamgreig a=therealprof Also this rectifies many of the tons of https://rust-lang.github.io/rust-clippy/master/index.html#identity_op lints we're getting. Signed-off-by: Daniel Egger <[email protected]> 346: Modernize svd2rust regress r=adamgreig a=therealprof A series of patches to bring it a bit more up-to-date. Includes: * making it Edition-2018 * bumping a few dependencies * fixing all clippy lints * changing to the master branch (instead of the ghost branch python-0.4 which can only be found by GitHub somehow) of the `cmsis-svd` repository * allowing `cargo init` on weirdly named SVD files * fixed NXP company name so SVD files can actually be downloaded * weeded out old STM SVD filenames and added some new ones Co-authored-by: Daniel Egger <[email protected]>
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Also this rectifies many of the tons of
https://rust-lang.github.io/rust-clippy/master/index.html#identity_op
lints we're getting.
Signed-off-by: Daniel Egger [email protected]