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Add codegen-llvm regression tests #145380
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rustbot has assigned @Mark-Simulacrum. Use |
// CHECK-LABEL: @is_inter_or_switch | ||
#[no_mangle] | ||
pub fn is_inter_or_switch(f: FrameType) -> bool { | ||
// CHECK-NOT: ADD |
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This feels a little brittle -- maybe we should check a more specific sequence of instructions? Or some other form of assertion that's not "no adds".
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Sure, I can change this to the specific sequence of checking and-cmp-ret in addition to the check-not.
This was the IR change from that issue, the subtraction being unwanted.
define i1 @src(i8 range(i8 0, 4) %arg) {
- %add = add nsw i8 %arg, -1
%and = and i8 %add, -3
%cmp = icmp eq i8 %and, 0
ret i1 %cmp
}
#[no_mangle] | ||
pub fn check_no_compare(v: &mut Vec<f32>) { | ||
// CHECK-NOT: icmp | ||
// CHECK-NOT: br |
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This also seems brittle -- I could see a future compiler making this just call Vec::clear
(given that the code sequence is the same for all 4-byte vec values, and maybe even for all T: Copy vec values?).
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I'm not sure what to do so I'll back this test out then.
1.29 codegen - https://rust.godbolt.org/z/9qcPPMh67
1.30 codegen - https://rust.godbolt.org/z/7qK1rojYG
Most of these regressions concern elimination of panics and bounds checks that were fixed upstream by LLVM.
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I removed the vec clear test and that issue from the PR message. @rustbot ready |
Most of these regressions deal with elimination of panics and bounds checks that were fixed upstream by LLVM.
closes #141497
closes #131162
closes #129583
closes #110971
closes #91109
closes #80075
closes #74917
closes #71997
closes #71257
closes #59352