rtl

Here are 147 public repositories matching this topic...

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Apr 29, 2025
Verilog

ultraembedded / cores

Sponsor

Star

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

open-sdr / openwifi-hw

Star

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

linux fpga zynq hls hardware vhdl rtl verilog xilinx sdr wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 mac80211

Updated Apr 18, 2025
Verilog

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

Updated Dec 6, 2024
Verilog

seldridge / verilog

Star

Repository for basic (and not so basic) Verilog blocks with high re-use potential

fpga hardware rtl verilog

Updated Mar 15, 2018
Verilog

The-OpenROAD-Project / OpenROAD-flow-scripts

Star

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Apr 29, 2025
Verilog

lastweek / fpga_readings

Star

Recipe for FPGA cooking

fpga hls rtl verilog xilinx vivado-hls

Updated Sep 29, 2024
Verilog

WangXuan95 / FPGA-ftdi245fifo

Star

An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

fpga usb rtl verilog systemverilog ft232h ipcore ft601 ft600

Updated May 21, 2024
Verilog

WangXuan95 / FPGA-SDcard-Reader

Star

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

fpga rtl verilog file-system systemverilog sd-card sdcard sdio

Updated Sep 14, 2023
Verilog

openasic-org / xkISP

Star

xkISP：Xinkai ISP IP Core (HLS)

fpga hls rtl isp

Updated Mar 14, 2023
Verilog

WangXuan95 / FPGA-CAN

Star

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

fpga controller rtl can verilog systemverilog can-bus control-area-network

Updated Sep 15, 2023
Verilog

WangXuan95 / FPGA-JPEG-LS-encoder

Star

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

fpga rtl verilog image-compression systemverilog image-encoder jpeg-ls jpegls jls

Updated Sep 18, 2024
Verilog

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

Star

IC implementation of Systolic Array for TPU

asic fpga rtl verilog asic-verification asic-design

Updated Oct 21, 2024
Verilog

WangXuan95 / FPGA-UART

Star

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

fpga rtl verilog uart

Updated Sep 14, 2023
Verilog

WangXuan95 / FPGA-FixedPoint

Star

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

pipeline rtl arithmetic verilog systemverilog fixedpoint

Updated Sep 14, 2023
Verilog

WangXuan95 / FPGA-DDR-SDRAM

Star

An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

fpga controller rtl verilog soft-core axi4 ddr-sdram ddr1

Updated Sep 15, 2023
Verilog

KASIRGA-KIZIL / tekno-kizil

Star

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

asic cpu fpga processor llvm verification clang riscv rtl verilog computer-architecture pipeline-processor in-order risc-v coremark rv32imc teknofest openlane

Updated Jul 20, 2023
Verilog

WangXuan95 / FPGA-SDfake

Star

Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。

fpga rtl verilog systemverilog sdcard sdio

Updated Sep 14, 2023
Verilog

WilsonChen003 / HDLGen

Star

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

python automation asic script perl rtl verilog hdl soc

Updated Oct 31, 2023
Verilog

michaelehab / AES-Verilog

Star

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

security cryptography encryption fpga aes rtl aes-256 aes-128 aes-192 verilog learn aes-encryption fpga-soc verilog-hdl encryption-decryption fpga-board aes-decryption verilog-project

Updated Jul 31, 2022
Verilog

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rtl

Here are 147 public repositories matching this topic...

The-OpenROAD-Project / OpenROAD

ultraembedded / cores

open-sdr / openwifi-hw

WangXuan95 / FPGA-USB-Device

seldridge / verilog

The-OpenROAD-Project / OpenROAD-flow-scripts

lastweek / fpga_readings

WangXuan95 / FPGA-ftdi245fifo

WangXuan95 / FPGA-SDcard-Reader

openasic-org / xkISP

WangXuan95 / FPGA-CAN

WangXuan95 / FPGA-JPEG-LS-encoder

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

WangXuan95 / FPGA-UART

WangXuan95 / FPGA-FixedPoint

WangXuan95 / FPGA-DDR-SDRAM

KASIRGA-KIZIL / tekno-kizil

WangXuan95 / FPGA-SDfake

WilsonChen003 / HDLGen

michaelehab / AES-Verilog

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