System Verilog BootCamp

learn the combinational and sequential logic circuit.

A project to implement a delayed feedback reservoir on the bladeRF 2.0 micro software defined radio (SDR) FPGA.

Counter that counts even numbers is created using a chain of eight D flip-flops. An OOP-based test bench and a package is developed to verify the counter's functionality as a black box and compare its output against the expected even number sequence. The design was implemented in two approaches i.e, asynchronous and synchronous structures.

Tea Encryption for ECE 4304 VHDL Design Project

VHDL implementation of VGA controller. Implemented on Zybo Zynq-7000 board which uses switches to change output color.

This project simules the basic functions of PIC16F84a.

A pipelined MIPS microprocessor written in VHDL and simulated in Xilinx Vivado targeting Basys3 board. Simplified MIPS instruction set. Made in RIT DSD2 (CMPE-260).

Vector ASIP for the application of filters to an image 🖼️

Rešenja zadataka sa vežbi iz predmeta "Projektovanje namenskih računarskih struktura 2"

SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial

Implementation of a FIR-filter on a FPGA and its employment in an audio system obtained using a PMOD I2S2.

A single SystemVerilog package with both classes of half as well as full adder is created and tested using the testbench

This repository serves as a collection of laboratory assignments completed during the "Basics of FPGA" course

A simple arithmetic logic unit (ALU) with System verilog

An 8-bit counter that counts from 0 to 255 when it is enabled and parallelly loaded. Structural approach is used here and treated as a black box and is verified using OOP based testbench.

My CMPE 691 491 Repo, I don't want to lose my school work code, so I back it up to here.

VGA Controller using FPGA / VHDL + game

Computer Architecture Lab - Assignments - Fall 2023