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Merged
merged 2 commits into from
Mar 22, 2025
Merged

[BACKEND] Bump to llvm/llvm-project@0ea4fb9 #6273

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3097ef9
[BACKEND] Bump to llvm/llvm-project@0ea4fb9
yiqian1 Mar 21, 2025
f2602f8
Merge branch 'main' into bump-llvm-0ea4fb9
antiagainst Mar 21, 2025
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2 changes: 1 addition & 1 deletion cmake/llvm-hash.txt
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Original file line number Diff line number Diff line change
@@ -1 +1 @@
2619c2ed584cdf3b38e6743ed3c785223f06e3f7
0ea4fb92648b2aa7cbab486bb493e122b4dcc062
6 changes: 3 additions & 3 deletions python/src/llvm.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,7 @@ createTargetMachine(llvm::Module *module, std::string proc,
opt.MCOptions.AsmVerbose = true;
opt.MCOptions.PreserveAsmComments = true;
std::unique_ptr<llvm::TargetMachine> machine{target->createTargetMachine(
module->getTargetTriple().str(), proc, features, opt, llvm::Reloc::PIC_,
module->getTargetTriple(), proc, features, opt, llvm::Reloc::PIC_,
std::nullopt,
disableLLVMOpt ? llvm::CodeGenOptLevel::None
: llvm::CodeGenOptLevel::Aggressive)};
Expand Down Expand Up @@ -277,8 +277,8 @@ void init_triton_llvm(py::module &&m) {
llvm::TargetOptions opt;
// Target machine is only used to create the data layout.
std::unique_ptr<llvm::TargetMachine> machine{target->createTargetMachine(
triple, proc, features, opt, llvm::Reloc::PIC_, std::nullopt,
llvm::CodeGenOptLevel::None)};
llvm::Triple(triple), proc, features, opt, llvm::Reloc::PIC_,
std::nullopt, llvm::CodeGenOptLevel::None)};
// set data layout
mod->setDataLayout(machine->createDataLayout());
});
Expand Down
48 changes: 24 additions & 24 deletions third_party/amd/lib/TritonAMDGPUToLLVM/ElementwiseOpToLLVM.cpp
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Expand Up @@ -37,8 +37,8 @@ cvtScalePkUpcastFromFp8(Location loc, ConversionPatternRewriter &rewriter,

auto resType = i32_ty;
auto dstType = f32_ty;
if constexpr (std::is_same_v<convertOp, ROCDL::CvtScale32PkF32Fp8> ||
std::is_same_v<convertOp, ROCDL::CvtScale32PkF32Bf8>) {
if constexpr (std::is_same_v<convertOp, ROCDL::CvtScaleF32PkF32Fp8Op> ||
std::is_same_v<convertOp, ROCDL::CvtScaleF32PkF32Bf8Op>) {
resType = i64_ty;
dstType = f32_ty;
} else {
Expand Down Expand Up @@ -70,8 +70,8 @@ cvtScalePkDowncastToFp8(Location loc, ConversionPatternRewriter &rewriter,
Value select = b.false_val();

Value result;
if constexpr (std::is_same_v<convertOp, ROCDL::CvtScaleF32PkFp8F32> ||
std::is_same_v<convertOp, ROCDL::CvtScaleF32PkBf8F32>) {
if constexpr (std::is_same_v<convertOp, ROCDL::CvtScaleF32PkFp8F32Op> ||
std::is_same_v<convertOp, ROCDL::CvtScaleF32PkBf8F32Op>) {
result = rewriter.create<convertOp>(loc, v2I16Ty, v2I16Vec, v0, v1, scale,
select);
} else {
Expand Down Expand Up @@ -134,8 +134,8 @@ static SmallVector<Value>
Fp16_to_Fp8E5M2_RTNE_HW(Location loc, ConversionPatternRewriter &rewriter,
const SmallVector<Value> &v) {
assert(v.size() == 2);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkBf8F16>(loc, rewriter,
v[0], v[1]);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkBf8F16Op>(loc, rewriter,
v[0], v[1]);
}

ConverterT Fp16_to_Fp8E5M2_RTNE(AMD::ISAFamily isaFamily) {
Expand Down Expand Up @@ -270,8 +270,8 @@ static SmallVector<Value>
Fp16_to_Fp8E4M3FN_RTNE_HW(Location loc, ConversionPatternRewriter &rewriter,
const SmallVector<Value> &v) {
assert(v.size() == 2);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkFp8F16>(loc, rewriter,
v[0], v[1]);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkFp8F16Op>(loc, rewriter,
v[0], v[1]);
}

ConverterT Fp16_to_Fp8E4M3FN_RTNE(AMD::ISAFamily isaFamily) {
Expand Down Expand Up @@ -378,35 +378,35 @@ static SmallVector<Value> Fp8E4M3FN_to_Fp32(Location loc,
ConversionPatternRewriter &rewriter,
const SmallVector<Value> &v) {
assert(v.size() == 2);
return cvtScalePkUpcastFromFp8<ROCDL::CvtScale32PkF32Fp8>(loc, rewriter, v[0],
v[1]);
return cvtScalePkUpcastFromFp8<ROCDL::CvtScaleF32PkF32Fp8Op>(loc, rewriter,
v[0], v[1]);
}

// Convert OCP Bf8 to Fp32 on CDNA4
static SmallVector<Value> Fp8E5M2_to_Fp32(Location loc,
ConversionPatternRewriter &rewriter,
const SmallVector<Value> &v) {
assert(v.size() == 2);
return cvtScalePkUpcastFromFp8<ROCDL::CvtScale32PkF32Bf8>(loc, rewriter, v[0],
v[1]);
return cvtScalePkUpcastFromFp8<ROCDL::CvtScaleF32PkF32Bf8Op>(loc, rewriter,
v[0], v[1]);
}

// Convert Fp32 to OCP Fp8 on CDNA4
static SmallVector<Value> Fp32_to_Fp8E4M3FN(Location loc,
ConversionPatternRewriter &rewriter,
const SmallVector<Value> &v) {
assert(v.size() == 2);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkFp8F32>(loc, rewriter,
v[0], v[1]);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkFp8F32Op>(loc, rewriter,
v[0], v[1]);
}

// Convert Fp32 to OCP Bf8 on CDNA4
static SmallVector<Value> Fp32_to_Fp8E5M2(Location loc,
ConversionPatternRewriter &rewriter,
const SmallVector<Value> &v) {
assert(v.size() == 2);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkBf8F32>(loc, rewriter,
v[0], v[1]);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkBf8F32Op>(loc, rewriter,
v[0], v[1]);
}

// Fp32 -> Nanoo Bf8 on CDNA3
Expand Down Expand Up @@ -549,8 +549,8 @@ static SmallVector<Value>
Fp8E4M3FN_to_Fp16_HW(Location loc, ConversionPatternRewriter &rewriter,
const SmallVector<Value> &v) {
assert(v.size() == 2);
return cvtScalePkUpcastFromFp8<ROCDL::CvtScaleF32PkF16Fp8>(loc, rewriter,
v[0], v[1]);
return cvtScalePkUpcastFromFp8<ROCDL::CvtScaleF32PkF16Fp8Op>(loc, rewriter,
v[0], v[1]);
}

ConverterT Fp8E4M3FN_to_Fp16(AMD::ISAFamily isaFamily) {
Expand Down Expand Up @@ -591,8 +591,8 @@ static SmallVector<Value>
Fp8E5M2_to_Fp16_HW(Location loc, ConversionPatternRewriter &rewriter,
const SmallVector<Value> &v) {
assert(v.size() == 2);
return cvtScalePkUpcastFromFp8<ROCDL::CvtScaleF32PkF16Bf8>(loc, rewriter,
v[0], v[1]);
return cvtScalePkUpcastFromFp8<ROCDL::CvtScaleF32PkF16Bf8Op>(loc, rewriter,
v[0], v[1]);
}

ConverterT Fp8E5M2_to_Fp16(AMD::ISAFamily isaFamily) {
Expand Down Expand Up @@ -851,8 +851,8 @@ static SmallVector<Value>
Bf16_to_Fp8E5M2_HW(Location loc, ConversionPatternRewriter &rewriter,
const SmallVector<Value> &v) {
assert(v.size() == 2);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkBf8Bf16>(loc, rewriter,
v[0], v[1]);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkBf8Bf16Op>(loc, rewriter,
v[0], v[1]);
}

static ConverterT Bf16_to_Fp8E5M2(AMD::ISAFamily isaFamily) {
Expand All @@ -864,8 +864,8 @@ static SmallVector<Value> Bf16_to_Fp8E4M3FN(Location loc,
ConversionPatternRewriter &rewriter,
const SmallVector<Value> &v) {
assert(v.size() == 2);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkFp8Bf16>(loc, rewriter,
v[0], v[1]);
return cvtScalePkDowncastToFp8<ROCDL::CvtScaleF32PkFp8Bf16Op>(loc, rewriter,
v[0], v[1]);
}

// fp8e4m3fn to bf16
Expand Down
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