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Replace deprecated usage of Vec(initVals) with VecInit(initVals). (#121)
* Replace deprecated usage of Vec(initVals) with VecInit(initVals). * Placate auto clone type (make class parameter immutable).
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5 files changed

+5
-5
lines changed

5 files changed

+5
-5
lines changed

src/main/scala/examples/Router.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ class Packet extends Bundle {
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*
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* @param n is the number of fanned outputs for the routed packet
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*/
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class RouterIO(n: Int) extends Bundle {
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class RouterIO(val n: Int) extends Bundle {
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val read_routing_table_request = DeqIO(new ReadCmd())
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val read_routing_table_response = EnqIO(UInt(Router.addressWidth.W))
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val load_routing_table_request = DeqIO(new WriteCmd())

src/main/scala/problems/VecShiftRegisterSimple.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ class VecShiftRegisterSimple extends Module {
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})
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val initValues = Seq.fill(4) { 0.U(8.W) }
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val delays = RegInit(Vec(initValues))
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val delays = RegInit(VecInit(initValues))
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// Implement below ----------
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src/main/scala/solutions/Mul.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ class Mul extends Module {
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for (i <- 0 until 16)
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for (j <- 0 until 16)
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mulsValues += (i * j).asUInt(8.W)
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val tbl = Vec(mulsValues)
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val tbl = VecInit(mulsValues)
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io.z := tbl((io.x << 4.U) | io.y)
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}

src/main/scala/solutions/VecShiftRegisterParam.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ class VecShiftRegisterParam(val n: Int, val w: Int) extends Module {
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})
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val initValues = Seq.fill(n) { 0.U(w.W) }
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val delays = RegInit(Vec(initValues))
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val delays = RegInit(VecInit(initValues))
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for (i <- n-1 to 1 by -1) {
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delays(i) := delays(i - 1)

src/main/scala/solutions/VecShiftRegisterSimple.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ class VecShiftRegisterSimple extends Module {
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})
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val initValues = Seq.fill(4) { 0.U(8.W) }
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val delays = RegInit(Vec(initValues))
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val delays = RegInit(VecInit(initValues))
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delays(0) := io.in
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delays(1) := delays(0)

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