SD Card Controller IP

A high-performance SD Card controller with APB interface supporting SD/SDHC/SDXC cards with SPI and SD modes, DMA support, and comprehensive error handling.

🚀 Features

• Protocol Support: SD 1.0/1.1, SDHC 2.0, SDXC 3.0, UHS-I support
• Interface Modes: SPI mode and SD mode operation
• APB Interface: Standard APB slave interface for easy integration
• DMA Support: Optional DMA controller for high-speed transfers
• Security: Hardware-based encryption and authentication
• Power Management: Dynamic voltage and frequency scaling
• Debug Interface: Comprehensive debugging and monitoring capabilities
• Performance Monitoring: Real-time performance metrics and optimization
• Error Handling: Robust error detection and recovery mechanisms
• Calibration Support: Automatic timing and signal calibration
• Test Interface: Built-in self-test and manufacturing test support
• Performance: Up to 104MB/s (UHS-I), 25MB/s (SD mode), 12.5MB/s (SPI mode)
• Target Platforms: ASIC (Sky130B) and FPGA (Xilinx, Intel)

📋 Specifications

• Clock Frequency: Up to 100MHz (system), 208MHz (SD UHS-I), 50MHz (SD mode), 25MHz (SPI mode)
• Data Transfer Rate: Up to 104MB/s (UHS-I), 25MB/s (SD mode), 12.5MB/s (SPI mode)
• Command Response Time: < 1μs typical
• Block Transfer Time: < 1ms per 512-byte block
• Power Consumption: < 50mW active, < 5mW idle
• Security: AES-256 encryption, SHA-256 authentication
• Debug Interface: Real-time monitoring and performance counters
• Error Handling: Comprehensive error detection and recovery
• Test Coverage: 95% functional coverage, 90% code coverage

🏗️ Architecture

The SD Card Controller consists of the following key modules:

• APB Interface: Standard APB slave interface
• Register File: Control and status register management
• Command Engine: SD command generation and response parsing
• Data Engine: Data block transmission/reception with CRC
• Clock Generator: Configurable SD card clock generation
• DMA Controller: Optional DMA support for high-speed transfers
• Power Controller: Dynamic power management and voltage scaling
• Security Controller: Hardware-based encryption and authentication
• Debug Controller: Comprehensive debugging and monitoring
• Test Controller: Built-in self-test and manufacturing test support
• Error Controller: Robust error detection and recovery
• Performance Controller: Real-time performance metrics
• Calibration Controller: Automatic timing and signal calibration
• Interrupt Controller: Event-driven interrupt generation
• Interface Module: SD card physical interface management

📖 Documentation

• Design Specification: Complete design specification
• Architecture Guide: Detailed architecture documentation with block diagrams
• Overview: High-level overview and use cases
• User Guide: Integration and usage instructions
• API Reference: Register map and programming interface
• Developer Guide: Development and integration guide

🔧 Quickstart

1. Clone the repository:

   git clone https://github.com/vyges/sd-card-controller-ip.git
   cd sd-card-controller-ip

2. Initialize the project:

   vyges init --interactive

3. Run simulation tests:

   vyges test --simulation

4. Synthesize for ASIC:

   vyges build --target asic

5. Synthesize for FPGA:

   vyges build --target fpga

🔌 Integration

Basic Instantiation

sd_card_controller sd_ctrl (
    .clk_i        (system_clk),
    .reset_n_i    (system_reset_n),
    .psel_i       (apb_psel),
    .penable_i    (apb_penable),
    .pwrite_i     (apb_pwrite),
    .paddr_i      (apb_paddr),
    .pwdata_i     (apb_pwdata),
    .prdata_o     (apb_prdata),
    .pready_o     (apb_pready),
    .pslverr_o    (apb_pslverr),
    .sd_clk_o     (sd_clk),
    .sd_cmd_io    (sd_cmd),
    .sd_data_io   (sd_data),
    .sd_cd_i      (sd_card_detect),
    .sd_wp_i      (sd_write_protect),
    .irq_o        (sd_interrupt),
    .debug_clk_o  (debug_clk),
    .debug_data_o (debug_data),
    .debug_valid_o(debug_valid),
    .test_mode_i  (test_mode),
    .test_clk_i   (test_clk),
    .test_data_i  (test_data),
    .test_valid_i (test_valid)
);

Pinout Table

Pin Name	Direction	Type	Description
clk_i	Input	Clock	System clock (100MHz max)
reset_n_i	Input	Reset	Active-low reset
psel_i	Input	Control	APB select signal
penable_i	Input	Control	APB enable signal
pwrite_i	Input	Control	APB write signal
paddr_i[11:0]	Input	Address	APB address bus
pwdata_i[31:0]	Input	Data	APB write data
prdata_o[31:0]	Output	Data	APB read data
pready_o	Output	Control	APB ready signal
pslverr_o	Output	Control	APB slave error
sd_clk_o	Output	Clock	SD card clock
sd_cmd_io	Bidirectional	Data	SD command line
sd_data_io[3:0]	Bidirectional	Data	SD data lines
sd_cd_i	Input	Status	Card detect signal
sd_wp_i	Input	Status	Write protect signal
irq_o	Output	Interrupt	Interrupt output
debug_clk_o	Output	Clock	Debug clock
debug_data_o[7:0]	Output	Data	Debug data
debug_valid_o	Output	Control	Debug valid
test_mode_i	Input	Control	Test mode enable
test_clk_i	Input	Clock	Test clock
test_data_i[7:0]	Input	Data	Test data
test_valid_i	Input	Control	Test valid

Register Map

Address	Register	Access	Description
0x000	CTRL	R/W	Control Register
0x004	STAT	R	Status Register
0x008	CLK_CFG	R/W	Clock Configuration
0x00C	PWR_CTRL	R/W	Power Control
0x010	CMD_REG	R/W	Command Register
0x014	CMD_ARG	R/W	Command Argument
0x018	CMD_RESP	R	Command Response
0x01C	DATA_BUF	R/W	Data Buffer
0x020	INT_EN	R/W	Interrupt Enable
0x024	INT_STAT	R	Interrupt Status
0x028	INT_CLR	W	Interrupt Clear
0x02C	DMA_CTRL	R/W	DMA Control
0x030	DMA_ADDR	R/W	DMA Address
0x034	DMA_LEN	R/W	DMA Length
0x038	SEC_CTRL	R/W	Security Control
0x03C	SEC_KEY	R/W	Security Key
0x040	DEBUG_CTRL	R/W	Debug Control
0x044	DEBUG_DATA	R	Debug Data
0x048	PERF_CTRL	R/W	Performance Control
0x04C	PERF_CNT	R	Performance Counter
0x050	ERR_CTRL	R/W	Error Control
0x054	ERR_STAT	R	Error Status

🧪 Testing

The project includes comprehensive testbenches and verification infrastructure:

• SystemVerilog Testbenches: Complete testbenches for all 16 modules
• Cocotb Python Testbenches: Python-based verification for all modules
• Unit Tests: Individual module verification with coverage
• Integration Tests: Interface integration verification
• Protocol Tests: SD card protocol compliance testing
• Performance Tests: Timing and throughput verification
• Error Tests: Error injection and recovery testing
• Security Tests: Encryption and authentication verification
• Automated Test Suite: Comprehensive test automation script

Test Infrastructure

• Top-level Testbench: tb/sv_tb/sd_card_controller_tb.sv
• Module Testbenches: 16 SystemVerilog testbenches in tb/sv_tb/
• Cocotb Tests: 16 Python testbenches in tb/cocotb/
• Test Automation: test/run_tests.sh with comprehensive validation
• CI/CD Pipeline: GitHub Actions with multiple simulators

Running Tests

# Run comprehensive test suite
./test/run_tests.sh

# Run specific simulator tests
cd tb
make SIM=iverilog run
make SIM=verilator run
make SIM=cocotb run

# Run individual test categories
make test
make lint
make coverage

📦 Supported Platforms

ASIC

• PDK: Sky130B
• Tools: OpenLane, Yosys, OpenROAD
• Clock: Up to 50MHz
• Area: ~0.05mm²

FPGA

• Boards: Arty-A7-35, compatible with CFU Playground
• Tools: Vivado, Quartus
• Clock: Up to 100MHz
• Resources: ~2000 LUTs, ~1500 FFs, 2 BRAMs

🤝 Contributing

1. Fork the repository
2. Create a feature branch
3. Make your changes
4. Add tests for new functionality
5. Ensure all tests pass
6. Submit a pull request

📄 License

This project is licensed under the Apache-2.0 License - see the LICENSE file for details.

🙏 Acknowledgments

• Built with the Vyges IP development ecosystem
• Follows Vyges conventions for hardware IP development

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Built with ❤️ by the Vyges team