xiph · SiarheiVolkau · Aug 17, 2025 · Aug 17, 2025 · Aug 17, 2025 · Aug 17, 2025
diff --git a/Makefile.mips b/Makefile.mips
diff --git a/celt/_kiss_fft_guts.h b/celt/_kiss_fft_guts.h
@@ -102,7 +102,7 @@
 #if defined(OPUS_ARM_INLINE_EDSP)
 #include "arm/kiss_fft_armv5e.h"
 #endif
-#if defined(MIPSr1_ASM)
+#if defined(__mips_dsp)
 #include "mips/kiss_fft_mipsr1.h"
 #endif
 

diff --git a/celt/arch.h b/celt/arch.h
@@ -121,7 +121,7 @@ void celt_fatal(const char *str, const char *file, int line)
 /* Set this if opus_int64 is a native type of the CPU. */
 /* Assume that all LP64 architectures have fast 64-bit types; also x86_64
    (which can be ILP32 for x32) and Win64 (which is LLP64). */
-#if defined(__x86_64__) || defined(__LP64__) || defined(_WIN64)
+#if defined(__x86_64__) || defined(__LP64__) || defined(_WIN64) || defined (__mips)
 #define OPUS_FAST_INT64 1
 #else
 #define OPUS_FAST_INT64 0

diff --git a/celt/celt.c b/celt/celt.c
@@ -54,7 +54,7 @@
 #define PACKAGE_VERSION "unknown"
 #endif
 
-#if defined(MIPSr1_ASM)
+#if defined(FIXED_POINT) && defined(__mips_dsp)
 #include "mips/celt_mipsr1.h"
 #endif
 

diff --git a/celt/fixed_generic.h b/celt/fixed_generic.h
@@ -200,7 +200,7 @@
 /** Divide a 32-bit value by a 32-bit value. Result fits in 32 bits */
 #define DIV32(a,b) (((opus_val32)(a))/((opus_val32)(b)))
 
-#if defined(MIPSr1_ASM)
+#if defined(__mips_dsp)
 #include "mips/fixed_generic_mipsr1.h"
 #endif
 

diff --git a/celt/mdct.c b/celt/mdct.c
@@ -53,7 +53,7 @@
 #include "mathops.h"
 #include "stack_alloc.h"
 
-#if defined(MIPSr1_ASM)
+#if defined(FIXED_POINT) && defined(__mips_dsp)
 #include "mips/mdct_mipsr1.h"
 #endif
 

diff --git a/celt/mips/celt_mipsr1.h b/celt/mips/celt_mipsr1.h
@@ -97,18 +97,17 @@ void comb_filter(opus_val32 *y, opus_val32 *x, int T0, int T1, int N,
    {
       opus_val16 f;
       opus_val32 res;
+      long long acc;
       f = MULT16_16_Q15(window[i],window[i]);
       x0= x[i-T1+2];
 
-      asm volatile("MULT $ac1, %0, %1" : : "r" ((int)MULT16_16_Q15((Q15ONE-f),g00)), "r" ((int)x[i-T0]));
-
-      asm volatile("MADD $ac1, %0, %1" : : "r" ((int)MULT16_16_Q15((Q15ONE-f),g01)), "r" ((int)ADD32(x[i-T0-1],x[i-T0+1])));
-      asm volatile("MADD $ac1, %0, %1" : : "r" ((int)MULT16_16_Q15((Q15ONE-f),g02)), "r" ((int)ADD32(x[i-T0-2],x[i-T0+2])));
-      asm volatile("MADD $ac1, %0, %1" : : "r" ((int)MULT16_16_Q15(f,g10)), "r" ((int)x2));
-      asm volatile("MADD $ac1, %0, %1" : : "r" ((int)MULT16_16_Q15(f,g11)), "r" ((int)ADD32(x3,x1)));
-      asm volatile("MADD $ac1, %0, %1" : : "r" ((int)MULT16_16_Q15(f,g12)), "r" ((int)ADD32(x4,x0)));
-
-      asm volatile("EXTR.W %0,$ac1, %1" : "=r" (res): "i" (15));
+      acc = __builtin_mips_mult((int)MULT16_16_Q15((Q15ONE-f),g00), (int)x[i-T0]);
+      acc = __builtin_mips_madd(acc, (int)MULT16_16_Q15((Q15ONE-f),g01), (int)ADD32(x[i-T0-1],x[i-T0+1]));
+      acc = __builtin_mips_madd(acc, (int)MULT16_16_Q15((Q15ONE-f),g02), (int)ADD32(x[i-T0-2],x[i-T0+2]));
+      acc = __builtin_mips_madd(acc, (int)MULT16_16_Q15(f,g10), (int)x2);
+      acc = __builtin_mips_madd(acc, (int)MULT16_16_Q15(f,g11), (int)ADD32(x3,x1));
+      acc = __builtin_mips_madd(acc, (int)MULT16_16_Q15(f,g12), (int)ADD32(x4,x0));
+      res = __builtin_mips_extr_w(acc, 15);
 
       y[i] = x[i] + res;
 
@@ -134,13 +133,14 @@ void comb_filter(opus_val32 *y, opus_val32 *x, int T0, int T1, int N,
    for (i=overlap;i<N;i++)
    {
       opus_val32 res;
+      long long acc;
       x0=x[i-T1+2];
 
-      asm volatile("MULT $ac1, %0, %1" : : "r" ((int)g10), "r" ((int)x2));
+      acc = __builtin_mips_mult((int)g10, (int)x2);
+      acc = __builtin_mips_madd(acc, (int)g11, (int)ADD32(x3,x1));
+      acc = __builtin_mips_madd(acc, (int)g12, (int)ADD32(x4,x0));
+      res = __builtin_mips_extr_w(acc, 15);
 
-      asm volatile("MADD $ac1, %0, %1" : : "r" ((int)g11), "r" ((int)ADD32(x3,x1)));
-      asm volatile("MADD $ac1, %0, %1" : : "r" ((int)g12), "r" ((int)ADD32(x4,x0)));
-      asm volatile("EXTR.W %0,$ac1, %1" : "=r" (res): "i" (15));
       y[i] = x[i] + res;
       x4=x3;
       x3=x2;

diff --git a/celt/mips/fixed_generic_mipsr1.h b/celt/mips/fixed_generic_mipsr1.h
@@ -35,92 +35,72 @@
 
 #undef MULT16_32_Q15_ADD
 static inline int MULT16_32_Q15_ADD(int a, int b, int c, int d) {
-    int m;
-    asm volatile("MULT $ac1, %0, %1" : : "r" ((int)a), "r" ((int)b));
-    asm volatile("madd $ac1, %0, %1" : : "r" ((int)c), "r" ((int)d));
-    asm volatile("EXTR.W %0,$ac1, %1" : "=r" (m): "i" (15));
-    return m;
+    long long acc = __builtin_mips_mult(a, b);
+    acc = __builtin_mips_madd(acc, c, d);
+    return __builtin_mips_extr_w(acc, 15);
 }
 
 #undef MULT16_32_Q15_SUB
 static inline int MULT16_32_Q15_SUB(int a, int b, int c, int d) {
-    int m;
-    asm volatile("MULT $ac1, %0, %1" : : "r" ((int)a), "r" ((int)b));
-    asm volatile("msub $ac1, %0, %1" : : "r" ((int)c), "r" ((int)d));
-    asm volatile("EXTR.W %0,$ac1, %1" : "=r" (m): "i" (15));
-    return m;
+    long long acc = __builtin_mips_mult(a, b);
+    acc = __builtin_mips_msub(acc, c, d);
+    return __builtin_mips_extr_w(acc, 15);
 }
 
 #undef MULT16_16_Q15_ADD
 static inline int MULT16_16_Q15_ADD(int a, int b, int c, int d) {
-    int m;
-    asm volatile("MULT $ac1, %0, %1" : : "r" ((int)a), "r" ((int)b));
-    asm volatile("madd $ac1, %0, %1" : : "r" ((int)c), "r" ((int)d));
-    asm volatile("EXTR.W %0,$ac1, %1" : "=r" (m): "i" (15));
-    return m;
+    long long acc = __builtin_mips_mult(a, b);
+    acc = __builtin_mips_madd(acc, c, d);
+    return __builtin_mips_extr_w(acc, 15);
 }
 
 #undef MULT16_16_Q15_SUB
 static inline int MULT16_16_Q15_SUB(int a, int b, int c, int d) {
-    int m;
-    asm volatile("MULT $ac1, %0, %1" : : "r" ((int)a), "r" ((int)b));
-    asm volatile("msub $ac1, %0, %1" : : "r" ((int)c), "r" ((int)d));
-    asm volatile("EXTR.W %0,$ac1, %1" : "=r" (m): "i" (15));
-    return m;
+    long long acc = __builtin_mips_mult(a, b);
+    acc = __builtin_mips_msub(acc, c, d);
+    return __builtin_mips_extr_w(acc, 15);
 }
 
 
 #undef MULT16_32_Q16
 static inline int MULT16_32_Q16(int a, int b)
 {
-    int c;
-    asm volatile("MULT $ac1,%0, %1" : : "r" (a), "r" (b));
-    asm volatile("EXTR.W %0,$ac1, %1" : "=r" (c): "i" (16));
-    return c;
+    long long acc = __builtin_mips_mult(a, b);
+    return __builtin_mips_extr_w(acc, 16);
 }
 
 #undef MULT16_32_P16
 static inline int MULT16_32_P16(int a, int b)
 {
-    int c;
-    asm volatile("MULT $ac1, %0, %1" : : "r" (a), "r" (b));
-    asm volatile("EXTR_R.W %0,$ac1, %1" : "=r" (c): "i" (16));
-    return c;
+    long long acc = __builtin_mips_mult(a, b);
+    return __builtin_mips_extr_r_w(acc, 16);
 }
 
 #undef MULT16_32_Q15
 static inline int MULT16_32_Q15(int a, int b)
 {
-    int c;
-    asm volatile("MULT $ac1, %0, %1" : : "r" (a), "r" (b));
-    asm volatile("EXTR.W %0,$ac1, %1" : "=r" (c): "i" (15));
-    return c;
+    long long acc = __builtin_mips_mult(a, b);
+    return __builtin_mips_extr_w(acc, 15);
 }
 
 #undef MULT32_32_Q31
 static inline int MULT32_32_Q31(int a, int b)
 {
-    int r;
-    asm volatile("MULT $ac1, %0, %1" : : "r" (a), "r" (b));
-    asm volatile("EXTR.W %0,$ac1, %1" : "=r" (r): "i" (31));
-    return r;
+    long long acc = __builtin_mips_mult(a, b);
+    return __builtin_mips_extr_w(acc, 31);
 }
 
 #undef PSHR32
 static inline int PSHR32(int a, int shift)
 {
-    int r;
-    asm volatile ("SHRAV_R.W %0, %1, %2" :"=r" (r): "r" (a), "r" (shift));
-    return r;
+    return __builtin_mips_shra_r_w(a, shift);
 }
 
 #undef MULT16_16_P15
 static inline int MULT16_16_P15(int a, int b)
 {
-    int r;
-    asm volatile ("mul %0, %1, %2" :"=r" (r): "r" (a), "r" (b));
-    asm volatile ("SHRA_R.W %0, %1, %2" : "+r" (r):  "0" (r), "i"(15));
-    return r;
+    int r = a * b;
+    return __builtin_mips_shra_r_w(r, 15);
 }
 
 #endif /* CELT_FIXED_GENERIC_MIPSR1_H */