stm32h7rs xspi Node with domain clock for peripheral clock configuration #88051
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FRASTM
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Can also select the HCLK 5 to be the domain clock of the XSPI peripheral: |
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rebase on d453fb9 |
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rebase on 88b108d (fixing typo and conflict) |
tmon-nordic
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erwango
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erwango
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etienne-lms
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gautierg-st
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| @@ -455,6 +461,10 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, | |||
| case STM32_CLOCK_BUS_AHB2: | |||
| case STM32_CLOCK_BUS_AHB3: | |||
| case STM32_CLOCK_BUS_AHB4: | |||
| #if defined(CONFIG_SOC_SERIES_STM32H7RSX) | |||
| /* HCLK5 i a possible source clock for some peripherals */ | |||
| case STM32_SRC_HCLK5: | |||
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STM32_SRC_HCLK1/2/3/4 and STM32_CLOCK_BUS_AHB5 cases are still missing in this function.
Add the definitions of the PLL2 and PLL3 outputs for the stm32H7RS mcus and the HCLK 5 which is clock source for the XSPI instance. and other HCLKn for other peripherals. Signed-off-by: Francois Ramu <[email protected]>
Defines the corresponding memory area of the MPU for the external NOR xspi node. Signed-off-by: Francois Ramu <[email protected]>
Add the XSPI 2 which is an octoSPI connection to a octo NOR flash MX25UW25645GXDI00 (256 Mbits, 1.8 V, 200 MHz, DTR, rww) on the nucleo_h7s3l8 board. Signed-off-by: Francois Ramu <[email protected]>
Add the XSPI 2 which is an octoSPI connection to a octo NOR flash mx66uw1g45 on the stm32h7s78_dk disco kit Signed-off-by: Francois Ramu <[email protected]>
FRASTM
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adding the HCLKn clocks |
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erwango
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| @@ -2068,6 +2073,11 @@ static int flash_stm32_xspi_init(const struct device *dev) | |||
| LOG_ERR("XSPI mode SPI|DUAL|QUAD/DTR is not valid"); | |||
| return -ENOTSUP; | |||
| } | |||
| #if defined(CONFIG_SOC_SERIES_STM32H7RSX) | |||
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Nitpicking: may I suggest an empty line above?
| .Refresh = 0, | ||
| #endif /* OCTOSPI_DCR4_REFRESH */ | ||
| #endif /* XSPI_DCR4_REFRESH */ |
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Default loading 0 values is not strictly needed. Maybe simpler if removed.
| slot0_partition: partition@0 { | ||
| label = "image-0"; | ||
| reg = <0x00000000 DT_SIZE_K(512)>; | ||
| }; |
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Prefer with an empty line before each subnodes.
| }; | ||
| storage_partition: partition@110000 { | ||
| label = "storage"; | ||
| reg = <0x00110000 DT_SIZE_K(64)>; |
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Intentionally waste the remaining of the internal flash? 64kB is not much. Maybe increase to 1 or 2 MByte, or even (DT_SIZE_M(30) - DT_SIZE_K(64)).
| slot0_partition: partition@0 { | ||
| label = "image-0"; | ||
| reg = <0x00000000 DT_SIZE_K(512)>; | ||
| }; |
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Add an empty line between each subnode.
etienne-lms
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May 21, 2025
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So quick! nevermind, we'll fix the DT later :-) |
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This PR is adding the xspi nodes to the stm32h7rs serie with domain clock configuration for the peripheral clock and the XSPIMgr clock
The XSPI peripheral is clocked by the STM32_SRC_PLL2_S and the PLL2 is enabled in the board device tree