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SoC: Intel: ADSP: enable instruction cache #92175

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Merged
merged 1 commit into from
Jun 27, 2025

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lyakh
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@lyakh lyakh commented Jun 25, 2025

All intel_adsp architectures have instruction cache. Selecting CPU_HAS_ICACHE fixes gdb memory writing problems.

All intel_adsp architectures have instruction cache. Selecting
CPU_HAS_ICACHE fixes gdb memory writing problems.

Signed-off-by: Guennadi Liakhovetski <[email protected]>
@github-actions github-actions bot added platform: Intel ADSP Intel Audio platforms size: XS A PR changing only a single line of code labels Jun 25, 2025
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Ack - it does indeed have I$
@dcpleung @peter-mitsis fyi.

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What was this breaking, out of curiosity?

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@softwarecki softwarecki left a comment

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I'm surprised that it wasn't active. I thought we have a piece of code executing from the cache while we memory is already turned...

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lyakh commented Jun 26, 2025

What was this breaking, out of curiosity?

@andyross gdb, because

#if defined(CONFIG_ICACHE) && defined(CONFIG_DCACHE)
and

zephyr/arch/Kconfig

Lines 1051 to 1053 in cf0f00d

config ICACHE
bool "Instruction cache (i-cache) support"
depends on CPU_HAS_ICACHE

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lyakh commented Jun 26, 2025

I'm surprised that it wasn't active. I thought we have a piece of code executing from the cache while we memory is already turned...

@softwarecki not sure if this is your question - but icache is indeed currently active and used on Intel ADSPs with SOF, we just failed to enable this Kconfig option

@danieldegrasse danieldegrasse merged commit 2502567 into zephyrproject-rtos:main Jun 27, 2025
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@lyakh lyakh deleted the icache branch June 30, 2025 05:45
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8 participants