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andrewrk opened this issue Feb 14, 2020 · 0 comments · Fixed by #8922
Closed

test disabled: atomicrmw with floats #4457

andrewrk opened this issue Feb 14, 2020 · 0 comments · Fixed by #8922
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arch-aarch64 64-bit ARM arch-arm 32-bit ARM arch-mips 32-bit and 64-bit MIPS arch-riscv 32-bit and 64-bit RISC-V bug Observed behavior contradicts documented or intended behavior
Milestone
0.8.0

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@andrewrk
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zig/test/stage1/behavior/atomics.zig

Lines 148 to 152 in 40b9db7

test "atomicrmw with floats" {
if (builtin.arch == .aarch64 or builtin.arch == .arm or builtin.arch == .riscv64)
return error.SkipZigTest;
testAtomicRmwFloat();
}

Related:
@andrewrk andrewrk added bug Observed behavior contradicts documented or intended behavior arch-aarch64 64-bit ARM arch-arm 32-bit ARM arch-riscv 32-bit and 64-bit RISC-V labels Feb 14, 2020
@andrewrk andrewrk added this to the 0.7.0 milestone Feb 14, 2020
@andrewrk andrewrk mentioned this issue Feb 14, 2020
Open
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@vielmetti vielmetti mentioned this issue Mar 10, 2020
Open
6 tasks
@LemonBoy LemonBoy mentioned this issue Mar 11, 2020
Merged
3 tasks
@andrewrk andrewrk added the arch-mips 32-bit and 64-bit MIPS label Mar 12, 2020
@andrewrk andrewrk modified the milestones: 0.7.0, 0.8.0 Oct 30, 2020
@andrewrk andrewrk modified the milestones: 0.8.0, 0.9.0 Nov 6, 2020
@andrewrk andrewrk modified the milestones: 0.9.0, 0.10.0 May 19, 2021
LemonBoy added a commit to LemonBoy/zig that referenced this issue May 28, 2021
@LemonBoy
stage1: Fix for atomicrmw xchg on fp types
e1cb3f1 
Bitcast the pointer and operands to integer types having the same size,
working around LLVM inability to lower a LL/SC operation when the
operands have floating-point types (and are reasonably sized).

Closes ziglang#4457
@LemonBoy LemonBoy mentioned this issue May 28, 2021
Merged
andrewrk pushed a commit that referenced this issue May 28, 2021
@LemonBoy @andrewrk
stage1: Fix for atomicrmw xchg on fp types
d3fb9f9 
Bitcast the pointer and operands to integer types having the same size,
working around LLVM inability to lower a LL/SC operation when the
operands have floating-point types (and are reasonably sized).

Closes #4457
@andrewrk andrewrk modified the milestones: 0.10.0, 0.8.0 May 28, 2021
@Vexu Vexu mentioned this issue Jun 13, 2021
Merged
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arch-aarch64 64-bit ARM arch-arm 32-bit ARM arch-mips 32-bit and 64-bit MIPS arch-riscv 32-bit and 64-bit RISC-V bug Observed behavior contradicts documented or intended behavior
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Milestone
0.8.0
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stage1: Fix for atomicrmw xchg on fp types LemonBoy/zig
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@andrewrk