stage2,aarch64: basic overflow arithmetic support #11574
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Great work on the extended test. I will do my best to make them pass for the Wasm backend on Friday. |
Add emitters for `smull`, `umull` and `tst (immediate)` instructions.
src/arch/aarch64/Emit.zig
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| .smulh => try emit.writeInstruction(Instruction.smulh(rrr.rd.to64(), rrr.rn.to64(), rrr.rm.to64())), | ||
| .smull => try emit.writeInstruction(Instruction.smull(rrr.rd.to64(), rrr.rn.to32(), rrr.rm.to32())), | ||
| .umulh => try emit.writeInstruction(Instruction.umulh(rrr.rd.to64(), rrr.rn.to64(), rrr.rm.to64())), | ||
| .umull => try emit.writeInstruction(Instruction.umull(rrr.rd.to64(), rrr.rn.to32(), rrr.rm.to32())), |
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The to32()s and to64()s should not be here. Mir should always consist of valid assembly instructions with valid register sizes and it should be CodeGens job to ensure that. Emit can assume that the register sizes are all valid and shouldn't need to change them
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Agreed 100%! Lemme fix this!
| try self.spillCompareFlagsIfOccupied(); | ||
| self.compare_flags_inst = null; | ||
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| // TODO this should really be put in a helper similar to `binOpRegister` |
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In collaboration with @joachimschmidt557
Checklist:
add_with_overflowsub_with_overflowshl_with_overflowmul_with_overflow@joachimschmidt557 and @Luukdegram - seems I have given our three more work as now only
aarch64backend (excluding LLVM ofc) passes extended@mulWithOverflowtests ;-)Unblocks the
aarch64part of @wsengir's #11316