std.Target: Remove more dead OS/architecture tags

lib/compiler/aro/aro/Compilation.zig

@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
             \\#define __sparc_v9__ 1
             \\
         ),
-        .sparc, .sparcel => try w.writeAll(
+        .sparc => try w.writeAll(
             \\#define __sparc__ 1
             \\#define __sparc 1
             \\
@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi
 
     if (system_defines_mode == .include_system_defines) {
         try buf.appendSlice(
-            \\#define __VERSION__ "Aro 
+            \\#define __VERSION__ "Aro
         ++ @import("../backend.zig").version_str ++ "\"\n" ++
             \\#define __Aro__
             \\

lib/compiler/aro/aro/Driver/GCCDetector.zig

@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
             biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
             biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
         },
-        .sparc, .sparcel => {
+        .sparc => {
             lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
             triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
             biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);

lib/compiler/aro/aro/target.zig

@@ -53,13 +53,12 @@ pub fn intPtrType(target: std.Target) Type {
         .xcore,
         .hexagon,
         .m68k,
-        .spir,
         .spirv32,
         .arc,
         .avr,
         => return .{ .specifier = .int },
 
-        .sparc, .sparcel => switch (target.os.tag) {
+        .sparc => switch (target.os.tag) {
             .netbsd, .openbsd => {},
             else => return .{ .specifier = .int },
         },
@@ -133,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
     return switch (target.cpu.arch) {
         .arm, .armeb => 4,
         .aarch64, .aarch64_be => 4,
-        .sparc, .sparcel, .sparc64 => 4,
+        .sparc, .sparc64 => 4,
         .riscv64 => 2,
         else => 1,
     };
@@ -427,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
         .powerpc64le => "elf64lppc",
         .riscv32 => "elf32lriscv",
         .riscv64 => "elf64lriscv",
-        .sparc, .sparcel => "elf32_sparc",
+        .sparc => "elf32_sparc",
         .sparc64 => "elf64_sparc",
         .loongarch32 => "elf32loongarch",
         .loongarch64 => "elf64loongarch",
@@ -467,13 +466,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .powerpcle,
         .riscv32,
         .sparc,
-        .sparcel,
         .thumb,
         .thumbeb,
         .x86,
         .xcore,
         .nvptx,
-        .spir,
         .kalimba,
         .lanai,
         .wasm32,
@@ -487,7 +484,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .aarch64_be => copy.cpu.arch = .armeb,
         .nvptx64 => copy.cpu.arch = .nvptx,
         .wasm64 => copy.cpu.arch = .wasm32,
-        .spir64 => copy.cpu.arch = .spir,
         .spirv64 => copy.cpu.arch = .spirv32,
         .loongarch64 => copy.cpu.arch = .loongarch32,
         .mips64 => copy.cpu.arch = .mips,
@@ -513,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .lanai,
         .m68k,
         .msp430,
-        .sparcel,
         .spu_2,
         .xcore,
         .xtensa,
@@ -526,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .bpfel,
         .nvptx64,
         .wasm64,
-        .spir64,
         .spirv64,
         .loongarch64,
         .mips64,
@@ -550,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .powerpcle => copy.cpu.arch = .powerpc64le,
         .riscv32 => copy.cpu.arch = .riscv64,
         .sparc => copy.cpu.arch = .sparc64,
-        .spir => copy.cpu.arch = .spir64,
         .spirv32 => copy.cpu.arch = .spirv64,
         .thumb => copy.cpu.arch = .aarch64,
         .thumbeb => copy.cpu.arch = .aarch64_be,
@@ -597,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .riscv64 => "riscv64",
         .sparc => "sparc",
         .sparc64 => "sparc64",
-        .sparcel => "sparcel",
         .s390x => "s390x",
         .thumb => "thumb",
         .thumbeb => "thumbeb",
@@ -607,8 +599,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .xtensa => "xtensa",
         .nvptx => "nvptx",
         .nvptx64 => "nvptx64",
-        .spir => "spir",
-        .spir64 => "spir64",
         .spirv32 => "spirv32",
         .spirv64 => "spirv64",
         .kalimba => "kalimba",
@@ -624,8 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 
     const llvm_os = switch (target.os.tag) {
         .freestanding => "unknown",
-        .ananas => "ananas",
-        .cloudabi => "cloudabi",
         .dragonfly => "dragonfly",
         .freebsd => "freebsd",
         .fuchsia => "fuchsia",

lib/compiler/aro/aro/toolchains/Linux.zig

@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
         .powerpc,
         .powerpcle,
         .sparc,
-        .sparcel,
         => return "lib32",
         else => {},
     }

lib/compiler_rt/atomics.zig

@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
     // On SPARC systems that lacks CAS and/or swap instructions, the only
     // available atomic operation is a test-and-set (`ldstub`), so we force
     // every atomic memory access to go through the lock.
-    .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
+    .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
 
     // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
     // and set this parameter accordingly.

lib/compiler_rt/clear_cache.zig

@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
         else => false,
     };
     const sparc = switch (arch) {
-        .sparc, .sparc64, .sparcel => true,
+        .sparc, .sparc64 => true,
         else => false,
     };
     const apple = switch (os) {