benchmark: fix build error on Cortex-M0 #76
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The timing code uses the DWT cycle counter which is an M3/M4 feature. For the sake of M0, use the mbed microsecond timer if DWT is not available.
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Please submit PR to mbed-os-workshop-17q2 branch (so we can use it this week). |
| @@ -179,6 +179,8 @@ | |||
| mbedtls_printf( "FAILED: -0x%04x\r\n", -ret ); | |||
| #endif | |||
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| #if defined(CoreDebug_DEMCR_TRCENA_Msk) && defined(DWT_CTRL_CYCCNTENA_Msk) | |||
| /* DWT cycle counter is available (Cortex-M3, Cortex-M4) */ | |||
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We shouldn't use different ways of measuring time. Using the same implementation will let us compare results across different platforms/MCUs.
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The code always prints kB/s. I only changed the additional printing of cycles/byte, which aren't meaningful across platforms. The only fully portable alternative is not to have a cycle count at all, AFAICT. So this is the best I know how to do at the moment, but I'm open to suggestions.
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I suggest we remove the usage of the cycle counter and use only one way of measuring time (which is supported across platforms).
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#79 removes the cycle counter altogether.
A return statement was missing in a benchmarking function.
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Rebased against workshop branch: PR #77 |
The timing code uses the DWT cycle counter which is an M3/M4 feature.
For the sake of M0, use the mbed microsecond timer if DWT is not available.
This commit addresses #74