benchmark: remove cycle counter #79
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The DWT cycle counter is only available on Cortex-M3 and Cortex-M4, so the code didn't even build for Cortex-M0 targets. Now the code only shows throughput in KB/s. This commit addresses ARMmbed#74
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LGTM |
yanesca
approved these changes
Apr 25, 2017
mazimkhan
suggested changes
Jun 1, 2017
| i * BUFSIZE / 1024, \ | ||
| ( mbedtls_timing_hardclock() - tsc ) / ( j * BUFSIZE ) ); \ | ||
| mbedtls_printf( "%9lu KB/s\r\n", \ | ||
| i * BUFSIZE / 1024 ); \ |
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Since we are changing prints we should also update examples log file for CI to pass https://github.com/ARMmbed/mbed-os-example-tls/blob/master/tests/benchmark.log
This was referenced Jun 7, 2017
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Closing this PR as #88 is a more complete version of the changes that includes docs and Ci logs updates. |
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The DWT cycle counter is only available on Cortex-M3 and Cortex-M4, so
the code didn't even build for Cortex-M0 targets. Now the code only
shows throughput in KB/s.
This commit addresses #74
This PR is an alternative to #77 which retains the cycle counter where available.