Verilog: fix for multi-ary binary primitive gates #885
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kroening
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tautschnig
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src/verilog/verilog_synthesis.cpp
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| irep_idt id = instance.type().id() == ID_bool | ||
| ? module | ||
| : dstringt{"bit" + id2string(module)}; |
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| : dstringt{"bit" + id2string(module)}; | |
| : irep_idt{"bit" + id2string(module)}; |
The Verilog binary primitive gates (or, and, etc.) can be multi-ary. This fixes the case when there are more than two inputs.
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The Verilog binary primitive gates (or, and, etc.) can be multi-ary. This fixes the case when there are more than two inputs.
Fixes #880.