[TableGen] Fix calculation of Lanemask for RCs with artificial subregs.

[sdesmalen-arm]

TableGen builds up a map of "SubRegIdx -> Subclass" where Subclass is the largest class where all registers have SubRegIdx as a sub-register. When SubRegIdx (vis-a-vis the sub-register) is artificial it should still include it in the map. This map is used in various places, including in the calculation of the Lanemask of a register class, which otherwise calculates an incorrect lanemask.

[llvmbot]

@llvm/pr-subscribers-llvm-regalloc

@llvm/pr-subscribers-tablegen

Author: Sander de Smalen (sdesmalen-arm)

Changes

TableGen builds up a map of "SubRegIdx -> Subclass" where Subclass is the largest class where all registers have SubRegIdx as a sub-register. When SubRegIdx (vis-a-vis the sub-register) is artificial it should still include it in the map. This map is used in various places, including in the calculation of the Lanemask of a register class, which otherwise calculates an incorrect lanemask.

---

Full diff: https://github.com/llvm/llvm-project/pull/114392.diff

2 Files Affected:

• (modified) llvm/test/TableGen/ArtificialSubregs.td (+2-2)
• (modified) llvm/utils/TableGen/Common/CodeGenRegisters.cpp (+4-6)

diff --git a/llvm/test/TableGen/ArtificialSubregs.td b/llvm/test/TableGen/ArtificialSubregs.td
index 9c3ffeef8926e3..de924ac5ec5cb1 100644
--- a/llvm/test/TableGen/ArtificialSubregs.td
+++ b/llvm/test/TableGen/ArtificialSubregs.td
@@ -92,7 +92,7 @@ def TestTarget : Target;
 // CHECK-NEXT: 	SpillSize: { Default:64 }
 // CHECK-NEXT: 	SpillAlignment: { Default:64 }
 // CHECK-NEXT: 	NumRegs: 3
-// CHECK-NEXT: 	LaneMask: 0000000000000008
+// CHECK-NEXT: 	LaneMask: 0000000000000088
 // CHECK-NEXT: 	HasDisjunctSubRegs: 1
 // CHECK-NEXT: 	CoveredBySubRegs: 1
 // CHECK-NEXT: 	Allocatable: 1
@@ -131,7 +131,7 @@ def TestTarget : Target;
 // CHECK-NEXT: 	SpillSize: { Default:128 }
 // CHECK-NEXT: 	SpillAlignment: { Default:128 }
 // CHECK-NEXT: 	NumRegs: 3
-// CHECK-NEXT: 	LaneMask: 0000000000000088
+// CHECK-NEXT: 	LaneMask: 0000000000000089
 // CHECK-NEXT: 	HasDisjunctSubRegs: 1
 // CHECK-NEXT: 	CoveredBySubRegs: 1
 // CHECK-NEXT: 	Allocatable: 1
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index e9f5a4c19471f2..121d231c60dd8b 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2296,10 +2296,8 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
     if (R->Artificial)
       continue;
     const CodeGenRegister::SubRegMap &SRM = R->getSubRegs();
-    for (auto I : SRM) {
-      if (!I.first->Artificial)
-        SRSets[I.first].push_back(R);
-    }
+    for (auto I : SRM)
+      SRSets[I.first].push_back(R);
   }
 
   for (auto I : SRSets)
@@ -2308,8 +2306,6 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
   // Find matching classes for all SRSets entries.  Iterate in SubRegIndex
   // numerical order to visit synthetic indices last.
   for (const auto &SubIdx : SubRegIndices) {
-    if (SubIdx.Artificial)
-      continue;
     SubReg2SetMap::const_iterator I = SRSets.find(&SubIdx);
     // Unsupported SubRegIndex. Skip it.
     if (I == SRSets.end())
@@ -2319,6 +2315,8 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
       RC->setSubClassWithSubReg(&SubIdx, RC);
       continue;
     }
+    if (SubIdx.Artificial)
+      continue;
     // This is a real subset.  See if we have a matching class.
     CodeGenRegisterClass *SubRC = getOrCreateSubClass(
         RC, &I->second, RC->getName() + "_with_" + I->first->getName());