AMDGPU: Replace <4 x i32> undef uses in tests with poison #130902

arsenm · 2025-03-12T06:27:41Z

Most of these are from resource descriptors.

arsenm · 2025-03-12T06:28:05Z

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llvmbot · 2025-03-12T06:29:49Z

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

Most of these are from resource descriptors.

Patch is 73.70 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/130902.diff

26 Files Affected:

(modified) llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll (+5-5)
(modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll (+17-17)
(modified) llvm/test/CodeGen/AMDGPU/else.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll (+22-22)
(modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll (+12-12)
(modified) llvm/test/CodeGen/AMDGPU/sgpr-copy.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/si-spill-cf.ll (+67-67)
(modified) llvm/test/CodeGen/AMDGPU/skip-if-dead.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/smrd.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/split-smrd.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll (+31-31)
(modified) llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll (+6-6)
(modified) llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll (+3-3)
(modified) llvm/test/CodeGen/AMDGPU/wave32.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/wqm.ll (+15-15)

diff --git a/llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll b/llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll
index 7e5a5302ac2e1..b913b5c3ab746 100644
--- a/llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll
+++ b/llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll
@@ -7,7 +7,7 @@
 ; GCN: buffer_store_dword v0
 define amdgpu_ps void @adjust_writemask_crash_0_nochain() #0 {
 main_body:
-  %tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
+  %tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
   %tmp1 = bitcast <2 x float> %tmp to <2 x i32>
   %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
   %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -23,7 +23,7 @@ main_body:
 ; GCN: buffer_store_dword v0
 define amdgpu_ps void @adjust_writemask_crash_1_nochain() #0 {
 main_body:
-  %tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
+  %tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
   %tmp1 = bitcast <2 x float> %tmp to <2 x i32>
   %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
   %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -39,7 +39,7 @@ main_body:
 ; GCN: buffer_store_dword v0
 define amdgpu_ps void @adjust_writemask_crash_0_chain() #0 {
 main_body:
-  %tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
+  %tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
   %tmp1 = bitcast <2 x float> %tmp to <2 x i32>
   %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
   %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -55,7 +55,7 @@ main_body:
 ; GCN: buffer_store_dword v0
 define amdgpu_ps void @adjust_writemask_crash_1_chain() #0 {
 main_body:
-  %tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
+  %tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
   %tmp1 = bitcast <2 x float> %tmp to <2 x i32>
   %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
   %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -66,7 +66,7 @@ main_body:
 
 define amdgpu_ps void @adjust_writemask_crash_0_v4() #0 {
 main_body:
-  %tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
+  %tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
   %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
   %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
   %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll
index cab8e0b8baaa5..5065f57c67dfd 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll
@@ -293,7 +293,7 @@ declare <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32>, i32, i32 immarg)
 ; CHECK-LABEL: {{^}}bitcast_v4f32_to_v2i64:
 ; CHECK: s_buffer_load_{{dwordx4|b128}}
 define <2 x i64> @bitcast_v4f32_to_v2i64(<2 x i64> %arg) {
-  %val = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> undef, i32 0, i32 0)
+  %val = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> poison, i32 0, i32 0)
   %cast = bitcast <4 x float> %val to <2 x i64>
   %div = udiv <2 x i64> %cast, %arg
   ret <2 x i64> %div
diff --git a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
index 0784d13e588d4..d198ec28f1602 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
+++ b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
@@ -8,8 +8,8 @@
 ; of which were in SGPRs.
 define amdgpu_vs float @main(i32 %v) {
 main_body:
-  %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 960, i32 0)
-  %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 976, i32 0)
+  %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 960, i32 0)
+  %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 976, i32 0)
   br i1 undef, label %ENDIF56, label %IF57
 
 IF57:                                             ; preds = %ENDIF
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
index 2464275a87992..646ea8a584f2b 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
@@ -143,32 +143,32 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
 ; GFX11-NEXT:    v_max_f32_e32 v0, 0, v1
 ; GFX11-NEXT:    ; return to shader part epilog
 .entry:
-  %0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
+  %0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
   %.i2243 = extractelement <3 x float> %0, i32 2
-  %1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 0, i32 0)
+  %1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 0, i32 0)
   %2 = shufflevector <3 x i32> %1, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
   %3 = bitcast <4 x i32> %2 to <4 x float>
   %.i2248 = extractelement <4 x float> %3, i32 2
   %.i2249 = fmul reassoc nnan nsz arcp contract afn float %.i2243, %.i2248
   %4 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
-  %5 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
+  %5 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
   %.i2333 = extractelement <3 x float> %5, i32 2
   %6 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
-  %7 = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 3, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
+  %7 = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 3, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
   %.i1408 = extractelement <2 x float> %7, i32 1
   %.i0364 = extractelement <2 x float> %7, i32 0
-  %8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
-  %9 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 112, i32 0)
+  %8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
+  %9 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 112, i32 0)
   %10 = shufflevector <3 x i32> %9, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
   %11 = bitcast <4 x i32> %10 to <4 x float>
   %.i2360 = extractelement <4 x float> %11, i32 2
   %.i2363 = fmul reassoc nnan nsz arcp contract afn float %.i2360, %8
-  %12 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 96, i32 0)
+  %12 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 96, i32 0)
   %13 = shufflevector <3 x i32> %12, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
   %14 = bitcast <4 x i32> %13 to <4 x float>
   %.i2367 = extractelement <4 x float> %14, i32 2
   %.i2370 = fmul reassoc nnan nsz arcp contract afn float %.i0364, %.i2367
-  %15 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 32, i32 0)
+  %15 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 32, i32 0)
   %16 = shufflevector <3 x i32> %15, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
   %17 = bitcast <4 x i32> %16 to <4 x float>
   %.i2373 = extractelement <4 x float> %17, i32 2
@@ -181,19 +181,19 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
   %.i2397 = fmul reassoc nnan nsz arcp contract afn float %.i2363, %18
   %.i2404 = fmul reassoc nnan nsz arcp contract afn float %.i2394, %4
   %.i2407 = fadd reassoc nnan nsz arcp contract afn float %.i2397, %.i2404
-  %20 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 92, i32 0)
+  %20 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 92, i32 0)
   %21 = bitcast i32 %20 to float
-  %22 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 124, i32 0)
+  %22 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 124, i32 0)
   %23 = bitcast i32 %22 to float
   %24 = fsub reassoc nnan nsz arcp contract afn float %21, %23
   %25 = fmul reassoc nnan nsz arcp contract afn float %.i1408, %24
   %26 = fadd reassoc nnan nsz arcp contract afn float %25, %23
-  %27 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 44, i32 0)
+  %27 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 44, i32 0)
   %28 = bitcast i32 %27 to float
   %29 = fsub reassoc nnan nsz arcp contract afn float %28, %26
   %30 = fmul reassoc nnan nsz arcp contract afn float %6, %29
   %31 = fadd reassoc nnan nsz arcp contract afn float %26, %30
-  %32 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 192, i32 0)
+  %32 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 192, i32 0)
   %33 = bitcast i32 %32 to float
   %34 = fadd reassoc nnan nsz arcp contract afn float %33, -1.000000e+00
   %35 = fmul reassoc nnan nsz arcp contract afn float %18, %34
@@ -207,16 +207,16 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
   %42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 undef, i32 undef, i32 0, <8 x i32> undef, i32 0, i32 0)
   %.i2521 = extractelement <3 x float> %42, i32 2
   %43 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
-  %44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
+  %44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
   %.i2465 = extractelement <3 x float> %44, i32 2
   %.i2466 = fmul reassoc nnan nsz arcp contract afn float %.i2465, %43
   %.i2469 = fmul reassoc nnan nsz arcp contract afn float %.i2415, %.i2466
-  %45 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 64, i32 0)
+  %45 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 64, i32 0)
   %46 = shufflevector <3 x i32> %45, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
   %47 = bitcast <4 x i32> %46 to <4 x float>
   %.i2476 = extractelement <4 x float> %47, i32 2
   %.i2479 = fmul reassoc nnan nsz arcp contract afn float %.i2476, %18
-  %48 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 80, i32 0)
+  %48 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 80, i32 0)
   %49 = shufflevector <3 x i32> %48, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
   %50 = bitcast <4 x i32> %49 to <4 x float>
   %.i2482 = extractelement <4 x float> %50, i32 2
@@ -224,12 +224,12 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
   %.i2488 = fmul reassoc nnan nsz arcp contract afn float %.i2249, %18
   %.i2491 = fmul reassoc nnan nsz arcp contract afn float %.i2485, %4
   %.i2494 = fadd reassoc nnan nsz arcp contract afn float %.i2479, %.i2491
-  %51 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
+  %51 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
   %.i2515 = extractelement <3 x float> %51, i32 2
   %.i2516 = fadd reassoc nnan nsz arcp contract afn float %.i2515, %.i2494
   %.i2522 = fadd reassoc nnan nsz arcp contract afn float %.i2521, %.i2516
   %.i2525 = fmul reassoc nnan nsz arcp contract afn float %.i2522, %43
-  %52 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 16, i32 0)
+  %52 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 16, i32 0)
   %53 = shufflevector <3 x i32> %52, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
   %54 = bitcast <4 x i32> %53 to <4 x float>
   %.i2530 = extractelement <4 x float> %54, i32 2
diff --git a/llvm/test/CodeGen/AMDGPU/else.ll b/llvm/test/CodeGen/AMDGPU/else.ll
index d3d4b860f9ac7..aa9bd0fa4d618 100644
--- a/llvm/test/CodeGen/AMDGPU/else.ll
+++ b/llvm/test/CodeGen/AMDGPU/else.ll
@@ -41,7 +41,7 @@ if:
 
 else:
   %c = fmul float %v, 3.0
-  %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
+  %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
   %v.else = extractelement <4 x float> %tex, i32 0
   br label %end
 
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll
index f0c3a493d05f1..692a33bd20ea9 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll
@@ -1781,7 +1781,7 @@ attributes #3 = { optnone noinline "amdgpu-no-completion-action" "amdgpu-no-defa
 !4 = !{!""}
 !5 = !{i32 undef, i32 1}
 !6 = !{i32 1, i32 2, i32 4}
-!7 = !{<4 x i32> undef, i32 0}
+!7 = !{<4 x i32> poison, i32 0}
 !8 = !{i32 8, i32 16, i32 32}
 !9 = !{!"char"}
 !10 = !{!"ushort2"}
diff --git a/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll b/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
index 3afa4eb5742b9..7169905ef6cde 100644
--- a/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
+++ b/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
@@ -185,7 +185,7 @@ sw.bb10:
 ; GCN-DAG: v_readlane_b32 s30, [[CSR_VGPR]],
 ; GCN: s_waitcnt vmcnt(0)
 ; GCN: s_setpc_b64 s[30:31]
-  call fastcc void @svm_node_closure_bsdf(ptr addrspace(1) null, ptr null, <4 x i32> zeroinitializer, ptr null, i32 undef, i8 undef, float undef, float undef, float undef, i1 undef, <4 x i32> undef, float undef, i32 undef, i1 undef, i1 undef, i1 undef, float undef, ptr addrspace(1) poison, ptr addrspace(1) poison, ptr addrspace(1) poison, i1 undef, ptr addrspace(1) poison, i32 undef, i1 undef, i32 undef, i64 undef, i32 undef)
+  call fastcc void @svm_node_closure_bsdf(ptr addrspace(1) null, ptr null, <4 x i32> zeroinitializer, ptr null, i32 undef, i8 undef, float undef, float undef, float undef, i1 undef, <4 x i32> poison, float undef, i32 undef, i1 undef, i1 undef, i1 undef, float undef, ptr addrspace(1) poison, ptr addrspace(1) poison, ptr addrspace(1) poison, i1 undef, ptr addrspace(1) poison, i32 undef, i1 undef, i32 undef, i64 undef, i32 undef)
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
index 955d8ae5cc054..107e0a5450a4c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
@@ -28,7 +28,7 @@ define amdgpu_ps float @test2() #0 {
   %live = call i1 @llvm.amdgcn.ps.live()
   %live.32 = zext i1 %live to i32
   %live.32.bc = bitcast i32 %live.32 to float
-  %t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %live.32.bc, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
+  %t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %live.32.bc, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
   %r = extractelement <4 x float> %t, i32 0
   ret float %r
 }
@@ -51,7 +51,7 @@ dead:
 end:
   %tc = phi i32 [ %in, %entry ], [ %tc.dead, %dead ]
   %tc.bc = bitcast i32 %tc to float
-  %t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tc.bc, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0
+  %t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tc.bc, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0) #0
   %r = extractelement <4 x float> %t, i32 0
   ret float %r
 }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
index 4d80e4ce5af14..491908088908a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
@@ -103,7 +103,7 @@ main_body:
 ;CHECK: buffer_atomic_add v0,
 define amdgpu_ps float @test4() {
 main_body:
-  %v = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 1, <4 x i32> undef, i32 4, i32 0, i32 0)
+  %v = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 1, <4 x i32> poison, i32 4, i32 0, i32 0)
   %v.float = bitcast i32 %v to float
   ret float %v.float
 }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
index 5fb50d7e8589a..09abebd638611 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
@@ -15,8 +15,8 @@ define amdgpu_ps float @test1(i32 inreg %idx0, i32 inreg %idx1) {
 ; CHECK-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; CHECK-NEXT:    ; return to shader part epilog
 main_body:
-  %src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
-  %src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
+  %src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> poison, i32 %idx0, i32 0, i32 0, i32 0)
+  %src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> poison, i32 %idx1, i32 0, i32 0, i32 0)
   %out = fadd float %src0, %src1
   %out.0 = call float @llvm.amdgcn.softwqm.f32(float %out)
   ret float %out.0
@@ -36,8 +36,8 @@ define amdgpu_ps float @test2(i32 inreg %idx0, i32 inreg %idx1) {
 ; CHECK-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; CHECK-NEXT:    ; return to shader part epilog
 main_body:
-  %src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
-  %src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
+  %src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> poison, i32 %idx0, i32 0, i32 0, i32 0)
+  %src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> poison, i32 %idx1, i32 0, i32 0, i32 0)
   %out = fadd float %src0, %src1
   %out.0 = bitcast float %out to i32
   %out.1 = call i32 @llvm.amdgcn.softwqm.i32(i32 %out.0)
@@ -62,10 +62,10 @@ define amdgpu_ps float @test_softwqm1(i32 inreg %idx0, i32 inreg %idx1) {
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    ; return to shader part epilog
 main_body:
-  %src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
-  %src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
+  %src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> poison, i32 %idx0, i32 0, i32 0, i32 0)
+  %src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> poison, i32 %idx1, i32 0, i32 0, i32 0)
   %temp = fadd float %src0, %src1
-  call void @llvm.amdgcn.struct.buffer.store.f32(float %temp, <4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
+  call void @llvm.amdgcn.struct.buffer.store.f32(float %temp, <4 x i3...
[truncated]

github-actions · 2025-03-12T06:31:06Z

⚠️ undef deprecator found issues in your code. ⚠️

You can test this locally with the following command:

git diff -U0 --pickaxe-regex -S '([^a-zA-Z0-9#_-]undef[^a-zA-Z0-9_-]|UndefValue::get)' b89ce1d737f79f94e16ba89d5532e4bab835c89e 8535bb8a383b08ddaeb6f8220d25d1722b3a48cf llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll llvm/test/CodeGen/AMDGPU/else.ll llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll llvm/test/CodeGen/AMDGPU/sgpr-copy.ll llvm/test/CodeGen/AMDGPU/si-spill-cf.ll llvm/test/CodeGen/AMDGPU/skip-if-dead.ll llvm/test/CodeGen/AMDGPU/smrd.ll llvm/test/CodeGen/AMDGPU/split-smrd.ll llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll llvm/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll llvm/test/CodeGen/AMDGPU/wave32.ll llvm/test/CodeGen/AMDGPU/wqm.ll

The following files introduce new uses of undef:

llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll
llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
llvm/test/CodeGen/AMDGPU/else.ll
llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
llvm/test/CodeGen/AMDGPU/wave32.ll
llvm/test/CodeGen/AMDGPU/wqm.ll

Undef is now deprecated and should only be used in the rare cases where no replacement is possible. For example, a load of uninitialized memory yields undef. You should use poison values for placeholders instead.

In tests, avoid using undef and having tests that trigger undefined behavior. If you need an operand with some unimportant value, you can add a new argument to the function and use that instead.

For example, this is considered a bad practice:

define void @fn() {
  ...
  br i1 undef, ...
}

Please use the following instead:

define void @fn(i1 %cond) {
  ...
  br i1 %cond, ...
}

Please refer to the Undefined Behavior Manual for more information.

arsenm · 2025-03-13T01:21:55Z

Merge activity

Mar 12, 9:21 PM EDT: A user started a stack merge that includes this pull request via Graphite.
Mar 12, 9:25 PM EDT: Graphite rebased this pull request as part of a merge.
Mar 12, 9:28 PM EDT: A user merged this pull request with Graphite.

Most of these are from resource descriptors.

This was referenced Mar 12, 2025

AMDGPU: Replace undef with poison in tests using insertvalue #130895

Merged

AMDGPU: Replace insertelement poison with insertelement undef #130896

Merged

AMDGPU: Replace tests using undef in shufflevector with poison #130899

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arsenm marked this pull request as ready for review March 12, 2025 06:29

arsenm added backend:AMDGPU llvm:globalisel labels Mar 12, 2025 — with Graphite App

arsenm requested review from jayfoad, krzysz00 and shiltian March 12, 2025 06:29

arsenm force-pushed the users/arsenm/amdgpu/replace-ptr-addrspace1-undef-with-poison branch from ee3af3d to d5e21c3 Compare March 12, 2025 08:00

arsenm force-pushed the users/arsenm/amdgpu/tests-replace-v4i32-undef-with-poison branch from 4a77200 to bee7d9e Compare March 12, 2025 08:00

arsenm force-pushed the users/arsenm/amdgpu/replace-ptr-addrspace1-undef-with-poison branch 2 times, most recently from 212be89 to ee004b3 Compare March 12, 2025 09:15

arsenm force-pushed the users/arsenm/amdgpu/tests-replace-v4i32-undef-with-poison branch from bee7d9e to 63d490d Compare March 12, 2025 09:15

shiltian approved these changes Mar 12, 2025

View reviewed changes

shiltian changed the title ~~AMDAMDGPU: Replace <4 x i32> undef uses in tests with poison~~ AMDGPU: Replace <4 x i32> undef uses in tests with poison Mar 12, 2025

arsenm force-pushed the users/arsenm/amdgpu/replace-ptr-addrspace1-undef-with-poison branch from ee004b3 to b89ce1d Compare March 12, 2025 13:47

arsenm force-pushed the users/arsenm/amdgpu/tests-replace-v4i32-undef-with-poison branch from 63d490d to 8535bb8 Compare March 12, 2025 13:48

arsenm force-pushed the users/arsenm/amdgpu/replace-ptr-addrspace1-undef-with-poison branch from b89ce1d to 37db9b5 Compare March 13, 2025 01:22

Base automatically changed from users/arsenm/amdgpu/replace-ptr-addrspace1-undef-with-poison to main March 13, 2025 01:25

AMDAMDGPU: Replace <4 x i32> undef uses in tests with poison

5ebe718

Most of these are from resource descriptors.

arsenm force-pushed the users/arsenm/amdgpu/tests-replace-v4i32-undef-with-poison branch from 8535bb8 to 5ebe718 Compare March 13, 2025 01:25

arsenm merged commit c182f40 into main Mar 13, 2025
5 of 10 checks passed

arsenm deleted the users/arsenm/amdgpu/tests-replace-v4i32-undef-with-poison branch March 13, 2025 01:28

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