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Mar 13, 2025
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AMDGPU: Replace <4 x i32> undef uses in tests with poison #130902

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10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll
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Expand Up @@ -7,7 +7,7 @@
; GCN: buffer_store_dword v0
define amdgpu_ps void @adjust_writemask_crash_0_nochain() #0 {
main_body:
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
Expand All @@ -23,7 +23,7 @@ main_body:
; GCN: buffer_store_dword v0
define amdgpu_ps void @adjust_writemask_crash_1_nochain() #0 {
main_body:
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
Expand All @@ -39,7 +39,7 @@ main_body:
; GCN: buffer_store_dword v0
define amdgpu_ps void @adjust_writemask_crash_0_chain() #0 {
main_body:
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
Expand All @@ -55,7 +55,7 @@ main_body:
; GCN: buffer_store_dword v0
define amdgpu_ps void @adjust_writemask_crash_1_chain() #0 {
main_body:
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
Expand All @@ -66,7 +66,7 @@ main_body:

define amdgpu_ps void @adjust_writemask_crash_0_v4() #0 {
main_body:
%tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
%tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp1 = bitcast <4 x float> %tmp to <4 x i32>
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll
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Expand Up @@ -293,7 +293,7 @@ declare <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32>, i32, i32 immarg)
; CHECK-LABEL: {{^}}bitcast_v4f32_to_v2i64:
; CHECK: s_buffer_load_{{dwordx4|b128}}
define <2 x i64> @bitcast_v4f32_to_v2i64(<2 x i64> %arg) {
%val = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> undef, i32 0, i32 0)
%val = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> poison, i32 0, i32 0)
%cast = bitcast <4 x float> %val to <2 x i64>
%div = udiv <2 x i64> %cast, %arg
ret <2 x i64> %div
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
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Expand Up @@ -8,8 +8,8 @@
; of which were in SGPRs.
define amdgpu_vs float @main(i32 %v) {
main_body:
%d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 960, i32 0)
%d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 976, i32 0)
%d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 960, i32 0)
%d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 976, i32 0)
br i1 undef, label %ENDIF56, label %IF57

IF57: ; preds = %ENDIF
Expand Down
34 changes: 17 additions & 17 deletions llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
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Expand Up @@ -143,32 +143,32 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
; GFX11-NEXT: v_max_f32_e32 v0, 0, v1
; GFX11-NEXT: ; return to shader part epilog
.entry:
%0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
%0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
%.i2243 = extractelement <3 x float> %0, i32 2
%1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 0, i32 0)
%1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 0, i32 0)
%2 = shufflevector <3 x i32> %1, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
%3 = bitcast <4 x i32> %2 to <4 x float>
%.i2248 = extractelement <4 x float> %3, i32 2
%.i2249 = fmul reassoc nnan nsz arcp contract afn float %.i2243, %.i2248
%4 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
%5 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
%5 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
%.i2333 = extractelement <3 x float> %5, i32 2
%6 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
%7 = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 3, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
%7 = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 3, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
%.i1408 = extractelement <2 x float> %7, i32 1
%.i0364 = extractelement <2 x float> %7, i32 0
%8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
%9 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 112, i32 0)
%8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
%9 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 112, i32 0)
%10 = shufflevector <3 x i32> %9, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
%11 = bitcast <4 x i32> %10 to <4 x float>
%.i2360 = extractelement <4 x float> %11, i32 2
%.i2363 = fmul reassoc nnan nsz arcp contract afn float %.i2360, %8
%12 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 96, i32 0)
%12 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 96, i32 0)
%13 = shufflevector <3 x i32> %12, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
%14 = bitcast <4 x i32> %13 to <4 x float>
%.i2367 = extractelement <4 x float> %14, i32 2
%.i2370 = fmul reassoc nnan nsz arcp contract afn float %.i0364, %.i2367
%15 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 32, i32 0)
%15 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 32, i32 0)
%16 = shufflevector <3 x i32> %15, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
%17 = bitcast <4 x i32> %16 to <4 x float>
%.i2373 = extractelement <4 x float> %17, i32 2
Expand All @@ -181,19 +181,19 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
%.i2397 = fmul reassoc nnan nsz arcp contract afn float %.i2363, %18
%.i2404 = fmul reassoc nnan nsz arcp contract afn float %.i2394, %4
%.i2407 = fadd reassoc nnan nsz arcp contract afn float %.i2397, %.i2404
%20 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 92, i32 0)
%20 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 92, i32 0)
%21 = bitcast i32 %20 to float
%22 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 124, i32 0)
%22 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 124, i32 0)
%23 = bitcast i32 %22 to float
%24 = fsub reassoc nnan nsz arcp contract afn float %21, %23
%25 = fmul reassoc nnan nsz arcp contract afn float %.i1408, %24
%26 = fadd reassoc nnan nsz arcp contract afn float %25, %23
%27 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 44, i32 0)
%27 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 44, i32 0)
%28 = bitcast i32 %27 to float
%29 = fsub reassoc nnan nsz arcp contract afn float %28, %26
%30 = fmul reassoc nnan nsz arcp contract afn float %6, %29
%31 = fadd reassoc nnan nsz arcp contract afn float %26, %30
%32 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 192, i32 0)
%32 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 192, i32 0)
%33 = bitcast i32 %32 to float
%34 = fadd reassoc nnan nsz arcp contract afn float %33, -1.000000e+00
%35 = fmul reassoc nnan nsz arcp contract afn float %18, %34
Expand All @@ -207,29 +207,29 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
%42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 undef, i32 undef, i32 0, <8 x i32> undef, i32 0, i32 0)
%.i2521 = extractelement <3 x float> %42, i32 2
%43 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
%44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
%44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
%.i2465 = extractelement <3 x float> %44, i32 2
%.i2466 = fmul reassoc nnan nsz arcp contract afn float %.i2465, %43
%.i2469 = fmul reassoc nnan nsz arcp contract afn float %.i2415, %.i2466
%45 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 64, i32 0)
%45 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 64, i32 0)
%46 = shufflevector <3 x i32> %45, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
%47 = bitcast <4 x i32> %46 to <4 x float>
%.i2476 = extractelement <4 x float> %47, i32 2
%.i2479 = fmul reassoc nnan nsz arcp contract afn float %.i2476, %18
%48 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 80, i32 0)
%48 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 80, i32 0)
%49 = shufflevector <3 x i32> %48, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
%50 = bitcast <4 x i32> %49 to <4 x float>
%.i2482 = extractelement <4 x float> %50, i32 2
%.i2485 = fsub reassoc nnan nsz arcp contract afn float %.i2482, %.i2479
%.i2488 = fmul reassoc nnan nsz arcp contract afn float %.i2249, %18
%.i2491 = fmul reassoc nnan nsz arcp contract afn float %.i2485, %4
%.i2494 = fadd reassoc nnan nsz arcp contract afn float %.i2479, %.i2491
%51 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
%51 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
%.i2515 = extractelement <3 x float> %51, i32 2
%.i2516 = fadd reassoc nnan nsz arcp contract afn float %.i2515, %.i2494
%.i2522 = fadd reassoc nnan nsz arcp contract afn float %.i2521, %.i2516
%.i2525 = fmul reassoc nnan nsz arcp contract afn float %.i2522, %43
%52 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 16, i32 0)
%52 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 16, i32 0)
%53 = shufflevector <3 x i32> %52, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
%54 = bitcast <4 x i32> %53 to <4 x float>
%.i2530 = extractelement <4 x float> %54, i32 2
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/else.ll
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Expand Up @@ -41,7 +41,7 @@ if:

else:
%c = fmul float %v, 3.0
%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
%v.else = extractelement <4 x float> %tex, i32 0
br label %end

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll
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Expand Up @@ -1781,7 +1781,7 @@ attributes #3 = { optnone noinline "amdgpu-no-completion-action" "amdgpu-no-defa
!4 = !{!""}
!5 = !{i32 undef, i32 1}
!6 = !{i32 1, i32 2, i32 4}
!7 = !{<4 x i32> undef, i32 0}
!7 = !{<4 x i32> poison, i32 0}
!8 = !{i32 8, i32 16, i32 32}
!9 = !{!"char"}
!10 = !{!"ushort2"}
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
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Expand Up @@ -185,7 +185,7 @@ sw.bb10:
; GCN-DAG: v_readlane_b32 s30, [[CSR_VGPR]],
; GCN: s_waitcnt vmcnt(0)
; GCN: s_setpc_b64 s[30:31]
call fastcc void @svm_node_closure_bsdf(ptr addrspace(1) null, ptr null, <4 x i32> zeroinitializer, ptr null, i32 undef, i8 undef, float undef, float undef, float undef, i1 undef, <4 x i32> undef, float undef, i32 undef, i1 undef, i1 undef, i1 undef, float undef, ptr addrspace(1) poison, ptr addrspace(1) poison, ptr addrspace(1) poison, i1 undef, ptr addrspace(1) poison, i32 undef, i1 undef, i32 undef, i64 undef, i32 undef)
call fastcc void @svm_node_closure_bsdf(ptr addrspace(1) null, ptr null, <4 x i32> zeroinitializer, ptr null, i32 undef, i8 undef, float undef, float undef, float undef, i1 undef, <4 x i32> poison, float undef, i32 undef, i1 undef, i1 undef, i1 undef, float undef, ptr addrspace(1) poison, ptr addrspace(1) poison, ptr addrspace(1) poison, i1 undef, ptr addrspace(1) poison, i32 undef, i1 undef, i32 undef, i64 undef, i32 undef)
ret void
}

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
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Expand Up @@ -28,7 +28,7 @@ define amdgpu_ps float @test2() #0 {
%live = call i1 @llvm.amdgcn.ps.live()
%live.32 = zext i1 %live to i32
%live.32.bc = bitcast i32 %live.32 to float
%t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %live.32.bc, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
%t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %live.32.bc, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
%r = extractelement <4 x float> %t, i32 0
ret float %r
}
Expand All @@ -51,7 +51,7 @@ dead:
end:
%tc = phi i32 [ %in, %entry ], [ %tc.dead, %dead ]
%tc.bc = bitcast i32 %tc to float
%t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tc.bc, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0
%t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tc.bc, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0) #0
%r = extractelement <4 x float> %t, i32 0
ret float %r
}
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
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Expand Up @@ -103,7 +103,7 @@ main_body:
;CHECK: buffer_atomic_add v0,
define amdgpu_ps float @test4() {
main_body:
%v = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 1, <4 x i32> undef, i32 4, i32 0, i32 0)
%v = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 1, <4 x i32> poison, i32 4, i32 0, i32 0)
%v.float = bitcast i32 %v to float
ret float %v.float
}
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