[CodeGen] For ad hoc aliasing, additional regUnits are needed to fix lanemask representation

[vg0204]

With ad-hoc aliasing, new register unit are defined for each leaf register nodes that uniquely identifies them, alongwith an additional register unit connecting them (in the ad hoc alias graph that shows the register overlap between the aliasing leaf register nodes)

It solves the issue of using the aliasing register as the immediate subregister of a register, thus need to have disjoint lanemask, which is now possible by virtue of uniquely defined register units. At the same time, aliasing is accounted by the shared register unit, having lanemask as 0x0 just as previously, not a problem now.

It fixes #138552 and acts as an alternative solution to #79835

[llvmbot]

@llvm/pr-subscribers-tablegen

Author: Vikash Gupta (vg0204)

Changes

With ad-hoc aliasing, new register unit are defined for each leaf register nodes that uniquely identifies them, alongwith an additional register unit connecting them (in the ad hoc alias graph that shows the register overlap between the aliasing leaf register nodes)

It solves the issue of using the aliasing register as the immediate subregister of a register, thus need to have disjoint lanemask, which is now possible by virtue of uniquely defined register units. At the same time, aliasing is accounted by the shared register unit, having lanemask as 0x0 just as previously, not a problem now.

It fixes #138552 and acts as an alternative solution to #79835

---

Full diff: https://github.com/llvm/llvm-project/pull/139206.diff

1 Files Affected:

• (modified) llvm/utils/TableGen/Common/CodeGenRegisters.cpp (+30-12)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 639f94f79ecd7..44005747f24df 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -424,20 +424,33 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
   // These units correspond to the maximal cliques in the register overlap
   // graph which is optimal.
   //
-  // When there is ad hoc aliasing, we simply create one unit per edge in the
-  // undirected ad hoc aliasing graph. Technically, we could do better by
-  // identifying maximal cliques in the ad hoc graph, but cliques larger than 2
-  // are extremely rare anyway (I've never seen one), so we don't bother with
-  // the added complexity.
+  // When there is ad hoc aliasing, while we create one unit per edge in the
+  // undirected ad hoc aliasing graph to represent aliasing, one unit per each
+  // node leaf register is needed extra to identify them uniquely, in case these
+  // aliasing register are used as subregister(with disjoint lanemasks) to have
+  // an accurate lanemask generation for these leaf register.
+  // For example, In VE, SX0 is made out of disjoint subregister SW0 & SF0
+  // respectively, where SF0 is an alias for SW0. So while 2 register units will
+  // uniquely define these 2 subregister, the shared register unit will account
+  // for aliasing.
+  //
+  // Technically, we could do better by identifying maximal cliques in the ad
+  // hoc graph, but cliques larger than 2 are extremely rare anyway (I've never
+  // seen one), so we don't bother with the added complexity.
   for (CodeGenRegister *AR : ExplicitAliases) {
     // Only visit each edge once.
     if (AR->SubRegsComplete)
       continue;
     // Create a RegUnit representing this alias edge, and add it to both
     // registers.
-    unsigned Unit = RegBank.newRegUnit(this, AR);
-    RegUnits.set(Unit);
-    AR->RegUnits.set(Unit);
+    unsigned SharedUnit = RegBank.newRegUnit(this, AR);
+    RegUnits.set(SharedUnit);
+    AR->RegUnits.set(SharedUnit);
+
+    // Create a RegUnit that now corresponds uniquely to each of the both
+    // alias leaf register nodes.
+    RegUnits.set(RegBank.newRegUnit(this));
+    AR->RegUnits.set(RegBank.newRegUnit(AR));
   }
 
   // Finally, create units for leaf registers without ad hoc aliases. Note that
@@ -2669,12 +2682,17 @@ CodeGenRegBank::computeCoveredRegisters(ArrayRef<const Record *> Regs) {
   return BV;
 }
 
-void CodeGenRegBank::printRegUnitNames(ArrayRef<unsigned> Units) const {
-  for (unsigned Unit : Units) {
+void CodeGenRegBank::printRegUnitName(unsigned Unit) const {
+  if (Unit < NumNativeRegUnits)
+    dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName();
+  else
+    dbgs() << " #" << Unit;
+
+  if (RegUnits[Unit].Roots[1]) {
     if (Unit < NumNativeRegUnits)
-      dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName();
+      dbgs() << '~' << RegUnits[Unit].Roots[1]->getName();
     else
-      dbgs() << " #" << Unit;
+      dbgs() << "~#" << Unit;
   }
   dbgs() << '\n';
 }

[jayfoad]

This could do with a test. See test/TableGen/ArtificialSubregs.td for example. If you extend the -register-info-debug to print regunits as well as subregs, then you can test this patch in the same kind of way.

[jayfoad]

This is assuming that a register that has aliases is also a leaf, i.e. it has no sburegs. I am not sure whether that is a valid assumption.

[vg0204]

This is assuming that a register that has aliases is also a leaf, i.e. it has no sburegs. I am not sure whether that is a valid assumption.

It should not have subregs at this point, as the register units are created corresponding only to leaf registers, while other regs (including aliases) inherit the regunits of their corresponding subregs. If you see few lines above this changes you would observe.

[jayfoad]

I am asking whether any target defines a register with both Aliases and SubRegs. Currently I don't think any in-tree target does that, but it seems like it should be possible (and maybe out-of-tree targets do it?). For example, if the VE register SW0 had subregs for its upper and lower 16 bit halves.

[jayfoad]

As an alternative implementation, could you simply move this block before the "Absent any ad hoc aliasing..." block?

[vg0204]

Why so? Because the handling of leaf register without ad hoc aliasing is really happening after this from line 456 if you see!

[jayfoad]

The current logic is:

1. Inherit regunits from subregs.
2. Add a regunit for each alias.
3. If we have no regunits after #⁠1 and #⁠2, it must be a leaf without aliases. Give it a new unique regunit.

I am suggesting swapping #⁠2 and #⁠3:

1. Inherit regunits from subregs.
2. If we have no regunits after #⁠1, it must be a leaf. Give it a new unique regunit.
3. Add a regunit for each alias.

I think this gives the desired behavior.

[vg0204]

This could do with a test. See test/TableGen/ArtificialSubregs.td for example. If you extend the -register-info-debug to print regunits as well as subregs, then you can test this patch in the same kind of way.

Sure, I'll look into it