Skip to content

[flang] update ppc lit tests after using vector.insert and vector.extract (NFC) #148775

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 1 commit into from
Jul 18, 2025
Merged

[flang] update ppc lit tests after using vector.insert and vector.extract (NFC) #148775

merged 1 commit into from
Jul 18, 2025

Conversation

kkwli
Copy link
Collaborator

@kkwli kkwli commented Jul 15, 2025

See #143272

@kkwli kkwli self-assigned this Jul 15, 2025
@llvmbot llvmbot added flang Flang issues not falling into any other category flang:fir-hlfir labels Jul 15, 2025
@llvmbot
Copy link
Member

llvmbot commented Jul 15, 2025

@llvm/pr-subscribers-flang-fir-hlfir

Author: Kelvin Li (kkwli)

Changes

See #143272

Patch is 56.02 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/148775.diff

6 Files Affected:

  • (modified) flang/test/Lower/PowerPC/ppc-vec-extract-elem-order.f90 (+3-2)
  • (modified) flang/test/Lower/PowerPC/ppc-vec-extract.f90 (+80-62)
  • (modified) flang/test/Lower/PowerPC/ppc-vec-insert-elem-order.f90 (+3-2)
  • (modified) flang/test/Lower/PowerPC/ppc-vec-insert.f90 (+80-62)
  • (modified) flang/test/Lower/PowerPC/ppc-vec-splat-elem-order.f90 (+1-1)
  • (modified) flang/test/Lower/PowerPC/ppc-vec-splat.f90 (+62-62)
diff --git a/flang/test/Lower/PowerPC/ppc-vec-extract-elem-order.f90 b/flang/test/Lower/PowerPC/ppc-vec-extract-elem-order.f90
index 73669c25b339e..d7d14581b4b7f 100644
--- a/flang/test/Lower/PowerPC/ppc-vec-extract-elem-order.f90
+++ b/flang/test/Lower/PowerPC/ppc-vec-extract-elem-order.f90
@@ -1,4 +1,4 @@
-! RUN: %flang_fc1 -flang-experimental-hlfir -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
+! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
 ! REQUIRES: target=powerpc{{.*}}
 
 !CHECK-LABEL: vec_extract_testr4i8
@@ -27,6 +27,7 @@ subroutine vec_extract_testi8i1(arg1, arg2, r)
 ! LLVMIR: %[[arg2:.*]] = load i8, ptr %{{[0-9]}}, align 1
 ! LLVMIR: %[[urem:.*]] = urem i8 %[[arg2]], 2
 ! LLVMIR: %[[sub:.*]] = sub i8 1, %[[urem]]
-! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[arg1]], i8 %[[sub]]
+! LLVMIR: %[[idx:.*]] = zext i8 %[[sub]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[arg1]], i64 %[[idx]]
 ! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8
 end subroutine vec_extract_testi8i1
diff --git a/flang/test/Lower/PowerPC/ppc-vec-extract.f90 b/flang/test/Lower/PowerPC/ppc-vec-extract.f90
index 0f279347b6b75..32c0dcfd66013 100644
--- a/flang/test/Lower/PowerPC/ppc-vec-extract.f90
+++ b/flang/test/Lower/PowerPC/ppc-vec-extract.f90
@@ -1,5 +1,5 @@
-! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-LE" %s
-! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-BE" %s
+! RUN: %flang_fc1 -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-LE" %s
+! RUN: %flang_fc1 -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-BE" %s
 ! REQUIRES: target=powerpc{{.*}}
 
 !-------------
@@ -19,8 +19,9 @@ subroutine vec_extract_testf32(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
 ! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 4
 ! LLVMIR-BE: %[[s:.*]] = sub i8 3, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i8 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i8 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[idx]]
 ! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4
 
   r = vec_extract(x, i2)
@@ -29,8 +30,9 @@ subroutine vec_extract_testf32(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
 ! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 4
 ! LLVMIR-BE: %[[s:.*]] = sub i16 3, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i16 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i16 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[idx]]
 ! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4
 
   r = vec_extract(x, i4)
@@ -39,18 +41,19 @@ subroutine vec_extract_testf32(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
 ! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 4
 ! LLVMIR-BE: %[[s:.*]] = sub i32 3, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i32 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i32 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[idx]]
 ! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4
 
   r = vec_extract(x, i8)
 
 ! LLVMIR: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
 ! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
-! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 4
-! LLVMIR-BE: %[[s:.*]] = sub i64 3, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[s]]
+! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 4
+! LLVMIR-BE: %[[idx:.*]] = sub i64 3, %[[u]]
+! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 4
+! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[idx]]
 ! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4
 end subroutine vec_extract_testf32
 
@@ -68,8 +71,9 @@ subroutine vec_extract_testf64(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
 ! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 2
 ! LLVMIR-BE: %[[s:.*]] = sub i8 1, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i8 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i8 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[idx]]
 ! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8
 
   r = vec_extract(x, i2)
@@ -78,8 +82,9 @@ subroutine vec_extract_testf64(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
 ! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 2
 ! LLVMIR-BE: %[[s:.*]] = sub i16 1, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i16 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i16 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[idx]]
 ! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8
 
 
@@ -89,18 +94,19 @@ subroutine vec_extract_testf64(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
 ! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 2
 ! LLVMIR-BE: %[[s:.*]] = sub i32 1, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i32 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i32 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[idx]]
 ! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8
 
   r = vec_extract(x, i8)
 
 ! LLVMIR: %[[x:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
 ! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
-! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 2
-! LLVMIR-BE: %[[s:.*]] = sub i64 1, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[s]]
+! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 2
+! LLVMIR-BE: %[[idx:.*]] = sub i64 1, %[[u]]
+! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 2
+! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[idx]]
 ! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8
 end subroutine vec_extract_testf64
 
@@ -118,8 +124,9 @@ subroutine vec_extract_testi8(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
 ! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 16
 ! LLVMIR-BE: %[[s:.*]] = sub i8 15, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i8 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i8 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1
 
   r = vec_extract(x, i2)
@@ -128,8 +135,9 @@ subroutine vec_extract_testi8(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
 ! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 16
 ! LLVMIR-BE: %[[s:.*]] = sub i16 15, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i16 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i16 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1
 
   r = vec_extract(x, i4)
@@ -138,18 +146,19 @@ subroutine vec_extract_testi8(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
 ! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 16
 ! LLVMIR-BE: %[[s:.*]] = sub i32 15, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i32 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i32 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1
 
   r = vec_extract(x, i8)
 
 ! LLVMIR: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
 ! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
-! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 16
-! LLVMIR-BE: %[[s:.*]] = sub i64 15, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[s]]
+! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 16
+! LLVMIR-BE: %[[idx:.*]] = sub i64 15, %[[u]]
+! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 16
+! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1
 end subroutine vec_extract_testi8
 
@@ -167,8 +176,9 @@ subroutine vec_extract_testi16(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
 ! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 8
 ! LLVMIR-BE: %[[s:.*]] = sub i8 7, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i8 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i8 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2
 
   r = vec_extract(x, i2)
@@ -177,8 +187,9 @@ subroutine vec_extract_testi16(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
 ! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 8
 ! LLVMIR-BE: %[[s:.*]] = sub i16 7, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i16 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i16 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2
 
   r = vec_extract(x, i4)
@@ -187,18 +198,19 @@ subroutine vec_extract_testi16(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
 ! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 8
 ! LLVMIR-BE: %[[s:.*]] = sub i32 7, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i32 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i32 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2
 
   r = vec_extract(x, i8)
 
 ! LLVMIR: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
 ! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
-! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 8
-! LLVMIR-BE: %[[s:.*]] = sub i64 7, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[s]]
+! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 8
+! LLVMIR-BE: %[[idx:.*]] = sub i64 7, %[[u]]
+! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 8
+! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2
 end subroutine vec_extract_testi16
 
@@ -216,8 +228,9 @@ subroutine vec_extract_testi32(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
 ! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 4
 ! LLVMIR-BE: %[[s:.*]] = sub i8 3, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i8 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i8 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4
 
   r = vec_extract(x, i2)
@@ -226,8 +239,9 @@ subroutine vec_extract_testi32(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
 ! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 4
 ! LLVMIR-BE: %[[s:.*]] = sub i16 3, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i16 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i16 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4
 
   r = vec_extract(x, i4)
@@ -236,18 +250,19 @@ subroutine vec_extract_testi32(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
 ! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 4
 ! LLVMIR-BE: %[[s:.*]] = sub i32 3, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i32 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i32 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4
 
   r = vec_extract(x, i8)
 
 ! LLVMIR: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 ! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
-! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 4
-! LLVMIR-BE: %[[s:.*]] = sub i64 3, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[s]]
+! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 4
+! LLVMIR-BE: %[[idx:.*]] = sub i64 3, %[[u]]
+! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 4
+! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4
 end subroutine vec_extract_testi32
 
@@ -265,8 +280,9 @@ subroutine vec_extract_testi64(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
 ! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 2
 ! LLVMIR-BE: %[[s:.*]] = sub i8 1, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i8 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i8 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8
 
   r = vec_extract(x, i2)
@@ -275,8 +291,9 @@ subroutine vec_extract_testi64(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
 ! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 2
 ! LLVMIR-BE: %[[s:.*]] = sub i16 1, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i16 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i16 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8
 
   r = vec_extract(x, i4)
@@ -285,17 +302,18 @@ subroutine vec_extract_testi64(x, i1, i2, i4, i8)
 ! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
 ! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 2
 ! LLVMIR-BE: %[[s:.*]] = sub i32 1, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i32 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i32 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
+! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8
 
   r = vec_extract(x, i8)
 
 ! LLVMIR: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 ! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
-! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 2
-! LLVMIR-BE: %[[s:.*]] = sub i64 1, %[[u]]
-! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[u]]
-! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[s]]
+! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 2
+! LLVMIR-BE: %[[idx:.*]] = sub i64 1, %[[u]]
+! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 2
+! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[idx]]
 ! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8
 end subroutine vec_extract_testi64
diff --git a/flang/test/Lower/PowerPC/ppc-vec-insert-elem-order.f90 b/flang/test/Lower/PowerPC/ppc-vec-insert-elem-order.f90
index f64df46f170ab..b30065d74e46b 100644
--- a/flang/test/Lower/PowerPC/ppc-vec-insert-elem-order.f90
+++ b/flang/test/Lower/PowerPC/ppc-vec-insert-elem-order.f90
@@ -1,4 +1,4 @@
-! RUN: %flang_fc1 -flang-experimental-hlfir -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
+! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
 ! REQUIRES: target=powerpc{{.*}}
 
 !CHECK-LABEL: vec_insert_testf32i64
@@ -31,6 +31,7 @@ subroutine vec_insert_testi64i8(v, x, i1, i2, i4, i8)
 ! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
 ! LLVMIR: %[[urem:.*]] = urem i8 %[[i1]], 2
 ! LLVMIR: %[[sub:.*]] = sub i8 1, %[[urem]]
-! LLVMIR: %[[r:.*]] = insertelement <2 x i64> %[[x]], i64 %[[v]], i8 %[[sub]]
+! LLVMIR: %[[idx:.*]] = zext i8 %[[sub]] to i64
+! LLVMIR: %[[r:.*]] = insertelement <2 x i64> %[[x]], i64 %[[v]], i64 %[[idx]]
 ! LLVMIR: store <2 x i64> %[[r]], ptr %{{[0-9]}}, align 16
 end subroutine vec_insert_testi64i8
diff --git a/flang/test/Lower/PowerPC/ppc-vec-insert.f90 b/flang/test/Lower/PowerPC/ppc-vec-insert.f90
index dd57fcc67be08..26bc7fc114cec 100644
--- a/flang/test/Lower/PowerPC/ppc-vec-insert.f90
+++ b/flang/test/Lower/PowerPC/ppc-vec-insert.f90
@@ -1,5 +1,5 @@
-! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-LE" %s
-! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-BE" %s
+! RUN: %flang_fc1 -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-LE" %s
+! RUN: %flang_fc1 -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-BE" %s
 ! REQUIRES: target=powerpc{{.*}}
 
 ! vec_insert
@@ -20,8 +20,9 @@ subroutine vec_insert_testf32(v, x, i1, i2, i4, i8)
 ! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
 ! LLVMIR: %[[urem:.*]] = urem i8 %[[i1]], 4
 ! LLVMIR-BE: %[[s:.*]] = sub i8 3, %[[urem]]
-! LLVMIR-LE: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i8 %[[urem]]
-! LLVMIR-BE: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i8 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[urem]] to i64
+! LLVMIR: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i64 %[[idx]]
 ! LLVMIR: store <4 x float> %[[r]], ptr %{{[0-9]}}, align 16
 
   r = vec_insert(v, x, i2)
@@ -31,8 +32,9 @@ subroutine vec_insert_testf32(v, x, i1, i2, i4, i8)
 ! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
 ! LLVMIR: %[[urem:.*]] = urem i16 %[[i2]], 4
 ! LLVMIR-BE: %[[s:.*]] = sub i16 3, %[[urem]]
-! LLVMIR-LE: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i16 %[[urem]]
-! LLVMIR-BE: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i16 %[[s]]
+! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
+! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[urem]] to i64
+! LLVMIR: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i64 %[[idx]]
 ! LLVMIR: store <4 x float> %[[r]], ptr %{{[0-9]}}, align 16
 
   r = vec_insert(v, x, i4)
@@ -42,8 +44,9 @@ subroutine vec_insert_testf32(v, x, i1, i2, i4, i8)
 ! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
...
[truncated]

@kkwli kkwli mentioned this pull request Jul 15, 2025
Merged
madanial0
madanial0 approved these changes Jul 15, 2025
View reviewed changes
Copy link
Contributor

@madanial0 madanial0 left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM!

@dcaballe dcaballe merged commit 2e67dcf into llvm:main Jul 18, 2025
12 checks passed
This was referenced Jul 23, 2025
Closed
Closed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

@madanial0 madanial0 madanial0 approved these changes

@DanielCChen DanielCChen Awaiting requested review from DanielCChen

@dcaballe dcaballe Awaiting requested review from dcaballe

Assignees

@kkwli kkwli

Labels

flang:fir-hlfir flang Flang issues not falling into any other category

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

4 participants

@kkwli @llvmbot @madanial0 @dcaballe