Mips: Switch to RegClassByHwMode

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

@@ -3706,7 +3706,9 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
   MCRegister TmpReg = DstReg;
 
   const MCInstrDesc &Desc = MII.get(OpCode);
-  int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
+  int16_t DstRegClass =
+      MII.getOpRegClassID(Desc.operands()[StartOp],
+                          STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo));
   unsigned DstRegClassID =
       getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
@@ -3834,7 +3836,10 @@ void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
   MCRegister TmpReg = DstReg;
 
   const MCInstrDesc &Desc = MII.get(OpCode);
-  int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
+  int16_t DstRegClass =
+      MII.getOpRegClassID(Desc.operands()[StartOp],
+                          STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo));
+
   unsigned DstRegClassID =
       getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||

llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

@@ -916,6 +916,33 @@ DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
   return MCDisassembler::Success;
 }
 
+// Tablegen emits references to these unimplemented functions due to usage of
+// RegClassByHwMode - it does not detect that the RegClassByHwMode decoders are
+// unused, which in turn use these register class decoders.
+static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
                                              const MCDisassembler *Decoder) {

llvm/lib/Target/Mips/MicroMipsInstrInfo.td

@@ -57,12 +57,6 @@ def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
   let PredicateMethod = "isMemWithGRPMM16Base";
 }
 
-// Define the classes of pointers used by microMIPS.
-// The numbers must match those in MipsRegisterInfo::MipsPtrClass.
-def ptr_gpr16mm_rc : PointerLikeRegClass<1>;
-def ptr_sp_rc : PointerLikeRegClass<2>;
-def ptr_gp_rc : PointerLikeRegClass<3>;
-
 class mem_mm_4_generic : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops ptr_gpr16mm_rc, simm4);
@@ -114,7 +108,7 @@ def mem_mm_gp_simm7_lsl2 : Operand<i32> {
 
 def mem_mm_9 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm9);
+  let MIOperandInfo = (ops mips_ptr_rc, simm9);
   let EncoderMethod = "getMemEncodingMMImm9";
   let ParserMatchClass = MipsMemSimmAsmOperand<9>;
   let OperandType = "OPERAND_MEMORY";
@@ -130,15 +124,15 @@ def mem_mm_11 : Operand<i32> {
 
 def mem_mm_12 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm12);
+  let MIOperandInfo = (ops mips_ptr_rc, simm12);
   let EncoderMethod = "getMemEncodingMMImm12";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
 }
 
 def mem_mm_16 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm16);
+  let MIOperandInfo = (ops mips_ptr_rc, simm16);
   let EncoderMethod = "getMemEncodingMMImm16";
   let DecoderMethod = "DecodeMemMMImm16";
   let ParserMatchClass = MipsMemSimmAsmOperand<16>;

llvm/lib/Target/Mips/Mips.td

@@ -212,6 +212,22 @@ def FeatureStrictAlign
     : SubtargetFeature<"strict-align", "StrictAlign", "true",
                        "Disable unaligned load store for r6">;
 
+//===----------------------------------------------------------------------===//
+// Mips Instruction Predicate Definitions.
+//===----------------------------------------------------------------------===//
+
+def IsPTR64bit    :   Predicate<"Subtarget->isABI_N64()">,
+                      AssemblerPredicate<(all_of FeaturePTR64Bit)>;
+def IsPTR32bit    :   Predicate<"!Subtarget->isABI_N64()">,
+                      AssemblerPredicate<(all_of (not FeaturePTR64Bit))>;
+
+//===----------------------------------------------------------------------===//
+// HwModes
+//===----------------------------------------------------------------------===//
+
+defvar MIPS32 = DefaultMode;
+def MIPS64 : HwMode<[IsPTR64bit]>;
+
 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
 //===----------------------------------------------------------------------===//

llvm/lib/Target/Mips/MipsInstrInfo.td

@@ -156,6 +156,8 @@ def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
 //===----------------------------------------------------------------------===//
 // Mips Instruction Predicate Definitions.
 //===----------------------------------------------------------------------===//
+// FIXME: Move to Mips.td
+
 def HasMips2     :    Predicate<"Subtarget->hasMips2()">,
                       AssemblerPredicate<(all_of FeatureMips2)>;
 def HasMips3_32  :    Predicate<"Subtarget->hasMips3_32()">,
@@ -188,10 +190,6 @@ def IsGP64bit    :    Predicate<"Subtarget->isGP64bit()">,
                       AssemblerPredicate<(all_of FeatureGP64Bit)>;
 def IsGP32bit    :    Predicate<"!Subtarget->isGP64bit()">,
                       AssemblerPredicate<(all_of (not FeatureGP64Bit))>;
-def IsPTR64bit    :   Predicate<"Subtarget->isABI_N64()">,
-                      AssemblerPredicate<(all_of FeaturePTR64Bit)>;
-def IsPTR32bit    :   Predicate<"!Subtarget->isABI_N64()">,
-                      AssemblerPredicate<(all_of (not FeaturePTR64Bit))>;
 def HasMips64    :    Predicate<"Subtarget->hasMips64()">,
                       AssemblerPredicate<(all_of FeatureMips64)>;
 def NotMips64    :    Predicate<"!Subtarget->hasMips64()">,
@@ -1125,7 +1123,7 @@ def InvertedImOperand64 : Operand<i64> {
 
 class mem_generic : Operand<iPTR> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm16);
+  let MIOperandInfo = (ops mips_ptr_rc, simm16);
   let EncoderMethod = "getMemEncoding";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
@@ -1136,7 +1134,7 @@ def mem : mem_generic;
 
 // MSA specific address operand
 def mem_msa : mem_generic {
-  let MIOperandInfo = (ops ptr_rc, simm10);
+  let MIOperandInfo = (ops mips_ptr_rc, simm10);
   let EncoderMethod = "getMSAMemEncoding";
 }
 
@@ -1145,21 +1143,21 @@ def simm12 : Operand<i32> {
 }
 
 def mem_simm9_exp : mem_generic {
-  let MIOperandInfo = (ops ptr_rc, simm9);
+  let MIOperandInfo = (ops mips_ptr_rc, simm9);
   let ParserMatchClass = MipsMemSimmPtrAsmOperand;
   let OperandNamespace = "MipsII";
   let OperandType = "OPERAND_MEM_SIMM9";
 }
 
 foreach I = {9, 10, 11, 12, 16} in
   def mem_simm # I : mem_generic {
-    let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm" # I));
+    let MIOperandInfo = (ops mips_ptr_rc, !cast<Operand>("simm" # I));
     let ParserMatchClass = MipsMemSimmAsmOperand<I>;
   }
 
 foreach I = {1, 2, 3} in
   def mem_simm10_lsl # I : mem_generic {
-    let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm10_lsl" # I));
+    let MIOperandInfo = (ops mips_ptr_rc, !cast<Operand>("simm10_lsl" # I));
     let EncoderMethod = "getMemEncoding<" # I  # ">";
     let ParserMatchClass = MipsMemSimmAsmOperand<10, I>;
   }
@@ -1170,13 +1168,13 @@ def mem_simmptr : mem_generic {
 
 def mem_ea : Operand<iPTR> {
   let PrintMethod = "printMemOperandEA";
-  let MIOperandInfo = (ops ptr_rc, simm16);
+  let MIOperandInfo = (ops mips_ptr_rc, simm16);
   let EncoderMethod = "getMemEncoding";
   let OperandType = "OPERAND_MEMORY";
 }
 
 def PtrRC : Operand<iPTR> {
-  let MIOperandInfo = (ops ptr_rc);
+  let MIOperandInfo = (ops mips_ptr_rc);
   let DecoderMethod = "DecodePtrRegisterClass";
   let ParserMatchClass = GPR32AsmOperand;
 }

llvm/lib/Target/Mips/MipsRegisterInfo.cpp

@@ -46,20 +46,8 @@ unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
 
 const TargetRegisterClass *
 MipsRegisterInfo::getPointerRegClass(unsigned Kind) const {
-  MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
-
-  switch (PtrClassKind) {
-  case MipsPtrClass::Default:
-    return ArePtrs64bit ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
-  case MipsPtrClass::GPR16MM:
-    return &Mips::GPRMM16RegClass;
-  case MipsPtrClass::StackPointer:
-    return ArePtrs64bit ? &Mips::SP64RegClass : &Mips::SP32RegClass;
-  case MipsPtrClass::GlobalPointer:
-    return ArePtrs64bit ? &Mips::GP64RegClass : &Mips::GP32RegClass;
-  }
-
-  llvm_unreachable("Unknown pointer kind");
+  assert(Kind == 0 && "this should only be used for default case");
+  return ArePtrs64bit ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
 }
 
 unsigned

llvm/lib/Target/Mips/MipsRegisterInfo.h

@@ -29,18 +29,6 @@ class MipsRegisterInfo : public MipsGenRegisterInfo {
   const bool ArePtrs64bit;
 
 public:
-  enum class MipsPtrClass {
-    /// The default register class for integer values.
-    Default = 0,
-    /// The subset of registers permitted in certain microMIPS instructions
-    /// such as lw16.
-    GPR16MM = 1,
-    /// The stack pointer only.
-    StackPointer = 2,
-    /// The global pointer only.
-    GlobalPointer = 3,
-  };
-
   explicit MipsRegisterInfo(const MipsSubtarget &STI);
 
   /// Get PIC indirect call register

llvm/lib/Target/Mips/MipsRegisterInfo.td

@@ -758,3 +758,19 @@ def MSA128DOpnd : RegisterOperand<MSA128D> {
 def MSA128CROpnd : RegisterOperand<MSACtrl> {
   let ParserMatchClass = MSACtrlAsmOperand;
 }
+
+def mips_ptr_rc : RegClassByHwMode<
+  [MIPS32, MIPS64],
+  [GPR32, GPR64]>;
+
+def ptr_gpr16mm_rc : RegClassByHwMode<
+  [MIPS32, MIPS64],
+  [GPRMM16, GPRMM16]>; // FIXME: Why even use this if it's just a constant
+
+def ptr_sp_rc : RegClassByHwMode<
+  [MIPS32, MIPS64],
+  [SP32, SP64]>;
+
+def ptr_gp_rc : RegClassByHwMode<
+  [MIPS32, MIPS64],
+  [GP32, GP64]>;