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define asynchronous interrupt priorities #802

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11 changes: 9 additions & 2 deletions Sdtrig.tex
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Expand Up @@ -115,8 +115,9 @@ \section{Priority}
& 3 & & icount \\
& 3 & & itrigger \\
& 3 & & mcontrol/mcontrol6 after \\
& & & \hspace{2em}(on previous instruction) \\
\hline
& & & \hspace{2em}(on previous instruction) \\ \hline
& & Asynchronous interrupt enabled by & \\
& & \hspace{2em}xRET or explicit CSR write & \\ \hline
& 3 & Instruction address breakpoint & mcontrol/mcontrol6 execute address before \\ \hline
& 12 & Instruction page fault & \\ \hline
& 1 & Instruction access fault & \\ \hline
Expand Down Expand Up @@ -156,6 +157,12 @@ \section{Priority}
trace actions when triggers with different actions are also firing is left to
the trace specification.

\begin{commentary}
Note that asynchronous interrupts are included in the priority table because, when
enabled by xRET or explicit CSR write instructions, these interrupts must be treated
as high priority events on the next instruction.
\end{commentary}

\section{Native Triggers}
\label{sec:nativetrigger}

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