[AArch64] Combine store (trunc X to <3 x i8>) to sequence of ST1.b #8052
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(cherry-picked from 8336515)
Extra tests for llvm#78637 llvm#78632 (cherry-picked from ff1cde5)
Extra tests for llvm#78637 llvm#78632 (cherry-picked from e7b4ff8)
Add extra tests with different load/store alignments for llvm#78637. (cherry-picked from 98509c7)
…lvm#78637) Improve codegen for (trunc X to <3 x i8>) by converting it to a sequence of 3 ST1.b, but first converting the truncate operand to either v8i8 or v16i8, extracting the lanes for the truncate results and storing them. At the moment, there are almost no cases in which such vector operations will be generated automatically. The motivating case is non-power-of-2 SLP vectorization: llvm#77790 PR: llvm#78637 (cherry-picked from eb678d8)
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@swift-ci please test |
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@swift-ci please test llvm |
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@swift-ci please test macos |
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Improve codegen for (trunc X to <3 x i8>) by converting it to a sequence
of 3 ST1.b, but first converting the truncate operand to either v8i8 or
v16i8, extracting the lanes for the truncate results and storing them.
At the moment, there are almost no cases in which such vector operations
will be generated automatically. The motivating case is non-power-of-2
SLP vectorization: llvm#77790
PR: llvm#78637
(cherry-picked from eb678d8)