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[AArch64] Combine store (trunc X to <3 x i8>) to sequence of ST1.b #8052

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Merged
merged 5 commits into from
Jan 26, 2024
Merged

[AArch64] Combine store (trunc X to <3 x i8>) to sequence of ST1.b #8052

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7431631
[AArch64] Add tests for operations on vectors with 3 elements.
fhahn Jan 18, 2024
8af7a14
[AArch64] Add vec3 load/store tests with GEPs with const offsets.
fhahn Jan 22, 2024
44f385a
[AArch64] Add vec3 tests with add between load and store.
fhahn Jan 23, 2024
3d6f586
[AArch64] Add vec3 tests with different load/store alignments.
fhahn Jan 24, 2024
25f139e
[AArch64] Combine store (trunc X to <3 x i8>) to sequence of ST1.b. (…
fhahn Jan 25, 2024
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50 changes: 50 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -20937,6 +20937,53 @@ static SDValue combineBoolVectorAndTruncateStore(SelectionDAG &DAG,
Store->getMemOperand());
}

// Combine store (trunc X to <3 x i8>) to sequence of ST1.b.
static SDValue combineI8TruncStore(StoreSDNode *ST, SelectionDAG &DAG,
const AArch64Subtarget *Subtarget) {
SDValue Value = ST->getValue();
EVT ValueVT = Value.getValueType();

if (ST->isVolatile() || !Subtarget->isLittleEndian() ||
Value.getOpcode() != ISD::TRUNCATE ||
ValueVT != EVT::getVectorVT(*DAG.getContext(), MVT::i8, 3))
return SDValue();

assert(ST->getOffset().isUndef() && "undef offset expected");
SDLoc DL(ST);
auto WideVT = EVT::getVectorVT(
*DAG.getContext(),
Value->getOperand(0).getValueType().getVectorElementType(), 4);
SDValue UndefVector = DAG.getUNDEF(WideVT);
SDValue WideTrunc = DAG.getNode(
ISD::INSERT_SUBVECTOR, DL, WideVT,
{UndefVector, Value->getOperand(0), DAG.getVectorIdxConstant(0, DL)});
SDValue Cast = DAG.getNode(
ISD::BITCAST, DL, WideVT.getSizeInBits() == 64 ? MVT::v8i8 : MVT::v16i8,
WideTrunc);

MachineFunction &MF = DAG.getMachineFunction();
SDValue Chain = ST->getChain();
MachineMemOperand *MMO = ST->getMemOperand();
unsigned IdxScale = WideVT.getScalarSizeInBits() / 8;
SDValue E2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i8, Cast,
DAG.getConstant(2 * IdxScale, DL, MVT::i64));
TypeSize Offset2 = TypeSize::getFixed(2);
SDValue Ptr2 = DAG.getMemBasePlusOffset(ST->getBasePtr(), Offset2, DL);
Chain = DAG.getStore(Chain, DL, E2, Ptr2, MF.getMachineMemOperand(MMO, 2, 1));

SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i8, Cast,
DAG.getConstant(1 * IdxScale, DL, MVT::i64));
TypeSize Offset1 = TypeSize::getFixed(1);
SDValue Ptr1 = DAG.getMemBasePlusOffset(ST->getBasePtr(), Offset1, DL);
Chain = DAG.getStore(Chain, DL, E1, Ptr1, MF.getMachineMemOperand(MMO, 1, 1));

SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i8, Cast,
DAG.getConstant(0, DL, MVT::i64));
Chain = DAG.getStore(Chain, DL, E0, ST->getBasePtr(),
MF.getMachineMemOperand(MMO, 0, 1));
return Chain;
}

static SDValue performSTORECombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
SelectionDAG &DAG,
Expand All @@ -20952,6 +20999,9 @@ static SDValue performSTORECombine(SDNode *N,
return EltVT == MVT::f32 || EltVT == MVT::f64;
};

if (SDValue Res = combineI8TruncStore(ST, DAG, Subtarget))
return Res;

// If this is an FP_ROUND followed by a store, fold this into a truncating
// store. We can do this even if this is already a truncstore.
// We purposefully don't care about legality of the nodes here as we know
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