HiFive1 rev B support

[aykevl]

https://wiki.osdev.org/HiFive-1_Bare_Bones

[aykevl]

Things that are needed for this to be mergeable:

• Add SiFive FE310 cmsis-svd/cmsis-svd#72
• Interrupts need to be fixed. The gen-device-svd.py file assumes that it should create ARM assembly which of course won't work on RISC-V. Also, RISC-V interrupts work slightly different.
• Preferably, main: use internal libclang to build C and assembly files #184 so that people do not have to build Clang with RISC-V support to use it.

There are more things (like time.Sleep/time.Now support, GPIO, other peripherals) that have not yet been implemented but they can happen at a later time.

[deadprogram]

Regarding the SVD file, I think we should run off our own fork of the cmsis-svd repo anyhow. We should also continue to submit upstream PRs as both you and I have been doing, but this allows us to not have to wait for the other maintainer, who seems somewhat busy.

Regarding the interrupts, and changes to the generator, we need to work on that part.

#184 you know I really want that anyhow. But we can incorporate that later, and continue to use the clang toolchain for now, right?

[aykevl]

#184 you know I really want that anyhow. But we can incorporate that later, and continue to use the clang toolchain for now, right?

Unfortunately, no. RISC-V is not included in most LLVM builds so people wouldn't be able to use an external clang, unless they compile LLVM manually.

[aykevl]

The upstream SVD file hangs on the fact that the license situation isn't entirely clear and that SiFive doesn't provide SVD files. I have posted here on the forum in the hope that it will help: https://forums.sifive.com/t/svd-file-for-e310-g000/731/11

[aykevl]

• switched to our own fork of cmsis-svd
• rebased on top of Add support for newer SVD files in cmsis-svd repository #439 to avoid problems parsing SVD files
• changed the compiler and linker to be from the riscv64-unknown-elf-* toolchain (provided by SiFive). This should be changed in the future, but is likely easier for users than requiring them to build Clang with RISC-V support.

[aykevl]

This pull request is now ready to merge.

[deadprogram]

I started to test this.

First, I obtained the SiFive GNU tools. Then updated the submodule to get the latest SVD files, and re-ran the generator. also used go install to rebuild tinygo itself. So far, so good.

I then ran into compilation problem:

$ tinygo build -size short -o test.elf -target=hifive1b            examples/blinky1
error: No available targets are compatible with triple "riscv32--none"

I think that indicates that my LLVM installation lacks the needed risc-v support, right?

EDITED to have better grammar and explanation.

[aykevl]

You need to rebuild LLVM, and then build it using make. This error indicates that you built without RISC-V support. I'm not aware of a LLVM build that includes RISC-V by default.

[deadprogram]

Can I just run our own make llvm-source; make llvm-build task to achieve this?

[aykevl]

Yes, just make llvm-build should be enough. But you probably need to remove (or move, to be safe) that directory first.

[deadprogram]

Added page at https://github.com/tinygo-org/tinygo/wiki/RISC-V to help anyone who want to experiement with this.

Now merging, great work @aykevl this is a massive step into the future.