Super scalar Processor design

Senior Design Project at UW-Madison ECE

A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines

A RISC custom-ISA, 16-Bit Processor

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

Single Bus Processor - Summer Project 2016

A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

Verilog implementation of a subset of MIPS 32 Bit Processor Instructions, ISA design, Assembler Design and Compiler design

This project involves the implementation and simulation of a MIPS 5-stage pipelined processor using Verilog. The implementation is based on the MIPS architecture as outlined in the "Computer Organization and Design: The Hardware/Software Interface" and "Digital Design and Computer Architecture"

A Three Stage Pipeline 16-bit processor implemented in Verilog

RISC-V CPU Base Integer 32 bit ISA Implementation in Verilog HDL (Singlecycle, Multicycle, Pipelined). Update with more extension functionalities in the future.

Sextium® III processor implemented in Verilog

Design and Implementation of 5 stage pipeline architecture using verilog

ARM processor pipeline implementation. Featuring hazard unit, forwarding unit, SRAM & cache memory.

Verilog RISC Processor Design

Full FPGA Implementation of 32-bit FSM-based Multi-State MIPS Processor

A functional processor in Verilog which supports the Y86-64 ISA with pipelining with hazard control.

This Verilog implementation represents a 32-bit MIPS processor featuring out-of-order execution.

This project implements a UART-controlled processing unit with dual clock domains for UART communication and datapath operations. A state machine decodes serial commands to control the datapath, enabling ALU operations, register file access, and data transmission. It's designed for embedded systems and educational purposes.

A Pipelined RISC-V Processor with forwarding support and hazard detection.