Replace deprecated usage of Vec(initVals) with VecInit(initVals).

src/main/scala/examples/Router.scala

@@ -32,7 +32,7 @@ class Packet extends Bundle {
   *
   * @param n is the number of fanned outputs for the routed packet
   */
-class RouterIO(n: Int) extends Bundle {
+class RouterIO(val n: Int) extends Bundle {
   val read_routing_table_request   = DeqIO(new ReadCmd())
   val read_routing_table_response  = EnqIO(UInt(Router.addressWidth.W))
   val load_routing_table_request   = DeqIO(new WriteCmd())

src/main/scala/problems/VecShiftRegisterSimple.scala

@@ -15,7 +15,7 @@ class VecShiftRegisterSimple extends Module {
   })
 
   val initValues = Seq.fill(4) { 0.U(8.W) }
-  val delays = RegInit(Vec(initValues))
+  val delays = RegInit(VecInit(initValues))
 
   // Implement below ----------
 

src/main/scala/solutions/Mul.scala

@@ -21,7 +21,7 @@ class Mul extends Module {
   for (i <- 0 until 16)
     for (j <- 0 until 16)
       mulsValues += (i * j).asUInt(8.W)
-  val tbl = Vec(mulsValues)
+  val tbl = VecInit(mulsValues)
   io.z := tbl((io.x << 4.U) | io.y)
 
 }

src/main/scala/solutions/VecShiftRegisterParam.scala

@@ -16,7 +16,7 @@ class VecShiftRegisterParam(val n: Int, val w: Int) extends Module {
   })
 
   val initValues = Seq.fill(n) { 0.U(w.W) }
-  val delays = RegInit(Vec(initValues))
+  val delays = RegInit(VecInit(initValues))
 
   for (i <- n-1 to 1 by -1) {
     delays(i) := delays(i - 1)

src/main/scala/solutions/VecShiftRegisterSimple.scala

@@ -15,7 +15,7 @@ class VecShiftRegisterSimple extends Module {
   })
 
   val initValues = Seq.fill(4) { 0.U(8.W) }
-  val delays = RegInit(Vec(initValues))
+  val delays = RegInit(VecInit(initValues))
 
   delays(0) := io.in
   delays(1) := delays(0)