Enable STM32L4R9i-disco DSI display via shield ST_B_DSI_MB1314

boards/shields/st_b_dsi_mb1314/Kconfig.shield

@@ -0,0 +1,6 @@
+# Copyright (c) 2025 STMicroelectronics
+
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_ST_B_DSI_MB1314
+	def_bool $(shields_list_contains,st_b_dsi_mb1314)

boards/shields/st_b_dsi_mb1314/boards/stm32l4r9i_disco.conf

@@ -0,0 +1,5 @@
+CONFIG_DISPLAY=y
+CONFIG_MIPI_DSI=y
+CONFIG_STM32_LTDC_RGB565=y
+CONFIG_STM32_LTDC_FB_NUM=1
+CONFIG_GPIO_HOGS_INIT_PRIORITY=71

boards/shields/st_b_dsi_mb1314/boards/stm32l4r9i_disco.overlay

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(16)>; /* 16MHz */
+	status = "okay";
+};
+
+&ltdc {
+	/* SRAM0 is too small to hold a framebuffer, use SRAM2 */
+	ext-sdram = <&sram2>;
+};
+
+&mfx {
+	dsi_3v3_pwron {
+		gpio-hog;
+		gpios = <8 GPIO_ACTIVE_LOW>;
+		output-high;
+		line-name = "DSI_3V3_PWRON";
+	};
+
+	dsi_1v8_pwron {
+		gpio-hog;
+		gpios = <18 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "DSI_1v8_PWRON";
+	};
+};
+
+&pllsai2 {
+	/* PLLSAI2 is here to generate the PCLK to feed the DSI
+	 * We need to feed roughly 500Mbps. PCLK depends on format
+	 * For 24bit (RGB888) format, we need roughly 20.8 MHz.  (Actually target 15 MHz)
+	 *   div-m = 1, mul-n = 60, div-r = 4, div-divr = 4
+	 *
+	 * PCLK = MSI (4MHz) * mul-n / (div-m * div-r * div-divr)
+	 */
+	status = "okay";
+	div-m = <1>;
+	mul-n = <60>;
+	div-r = <4>;
+	div-divr = <4>;
+	clocks = <&clk_msi>;
+};

boards/shields/st_b_dsi_mb1314/doc/index.rst

@@ -0,0 +1,45 @@
+.. _st_b_dsi_mb1314:
+
+ST B-DSI-MB1314
+###############
+
+Overview
+********
+
+This shield provides a DSI display, based on a round AMOLED touch-sensitive panel
+of 1.2 inches and 390x390 pixels. The display module reference is IEG1120TB103GF-001
+from Govisionox Optoelectronics. It displays up to 16M colors.
+
+.. figure:: mb1314.webp
+   :alt: B-DSI-MB1314 Image
+   :align: center
+
+   B-DSI-MB1314 Image
+
+Requirements
+************
+
+Your board needs to have ``zephyr_mipi_dsi`` and ``zephyr_lcd_controller``
+device-tree labels to work with this shield.
+
+Usage
+*****
+
+The shield can be used in any application by setting ``SHIELD`` to
+``st_b_dsi_mb1314`` and adding the necessary board specific device tree
+properties.
+
+Set ``--shield "st_b_dsi_mb1314"`` when you invoke ``west build``. For example:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/display
+   :board: stm32l4r9i_disco
+   :shield: st_b_dsi_mb1314
+   :goals: build
+
+References
+**********
+
+- `Product page <https://www.st.com/en/evaluation-tools/32l4r9idiscovery.html>`_
+
+- `User manual <https://www.st.com/resource/en/user_manual/um2271-discovery-kit-with-stm32l4r9ai-mcu-stmicroelectronics.pdf>`_

boards/shields/st_b_dsi_mb1314/shield.yml

@@ -0,0 +1,6 @@
+shield:
+  name: st_b_dsi_mb1314
+  full_name: ST B-DSI-MB1314
+  vendor: st
+  supported_features:
+    - display

boards/shields/st_b_dsi_mb1314/st_b_dsi_mb1314.overlay

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
+
+/ {
+	chosen {
+		zephyr,display = &zephyr_lcd_controller;
+	};
+};
+
+&zephyr_mipi_dsi {
+	status = "okay";
+
+	/* DSI HOST dedicated PLL to generate 62.5 MHz from 16MHz
+	 * source clock, in order to generate 500Mbps on single lane
+	 *
+	 * F_VCO = CLK_IN / pll-idf * 2 * pll-ndiv
+	 * PHI = F_VCO / 2 / (1 << pll-odf) = lane_byte_clk
+	 *     = 25 MHz / 5 * 2 * 100 / 2 / (1<<0) / 8 = 62.5 MHz
+	 */
+	pll-ndiv = <125>;
+	pll-idf = <4>;
+	pll-odf = <0>;
+
+	phy-timings = <33 /* ClockLaneHS2LPTime */
+		       30 /* ClockLaneLP2HSTime */
+		       11 /* DataLaneHS2LPTime */
+		       21 /* DataLaneLP2HSTime */
+		       0 /* DataLaneMaxReadTime */
+		       7 /* StopWaitTime */>;
+
+	host-timeouts = <1 /* TimeoutCkdiv */
+			 0 /* HighSpeedTransmissionTimeout */
+			 0 /* LowPowerReceptionTimeout */
+			 0 /* HighSpeedReadTimeout */
+			 0 /* LowPowerReadTimeout */
+			 0 /* HighSpeedWriteTimeout */
+			 0 /* HighSpeedWritePrespMode */
+			 0 /* LowPowerWriteTimeout */
+			 0 /* BTATimeout */>;
+
+	vs-active-high;
+	hs-active-high;
+	de-active-high;
+
+	lp-rx-filter=<10000>;
+
+	g1120tb101: panel@0 {
+		compatible = "gvo,g1120tb101";
+		reg = <0x0>;
+		height = <390>;
+		width = <390>;
+		data-lanes = <1>;
+		reset-gpios = <&dsi_lcd_qsh_030 57 GPIO_ACTIVE_LOW>;
+
+		pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
+	};
+};
+
+&zephyr_lcd_controller {
+	status = "okay";
+
+	width = <390>;
+	height = <390>;
+	pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
+
+	display-timings {
+		compatible = "zephyr,panel-timing";
+		de-active = <0>;
+		pixelclk-active = <0>;
+		hsync-active = <0>;
+		vsync-active = <0>;
+		hsync-len = <1>;
+		vsync-len = <1>;
+		hback-porch = <1>;
+		vback-porch = <1>;
+		hfront-porch = <1>;
+		vfront-porch = <1>;
+	};
+	def-back-color-red = <0x0>;
+	def-back-color-green = <0x0>;
+	def-back-color-blue = <0x0>;
+};

boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts

@@ -90,6 +90,24 @@
 			   <27 0 &gpioc 6 0>;  /* DCMI_D0 */
 	};
 
+	dsi_lcd_qsh_030: connector_dsi_lcd {
+		compatible = "st,dsi-lcd-qsh-030";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <4 0 &mfx 9 0>,	/* TOUCH_INT */
+			   <22 0 &gpioh 14 0>,  /* SPI_CS */
+			   <24 0 &gpiob 13 0>,  /* SPI2_SCK */
+			   <26 0 &gpiob 15 0>,  /* SPI2_MOSI */
+			   <28 0 &gpiob 14 0>,  /* SPI_DCX */
+			   <40 0 &gpiog 13 0>,	/* I2C1_SDA */
+			   <43 0 &gpioa 8 0>,	/* DSI_SWIRE */
+			   <44 0 &gpiob 6 0>,	/* I2C1_SCL */
+			   <49 0 &gpiof 11 0>,	/* DSI_TE */
+			   <53 0 &gpiob 1 0>,	/* LCD_BL_CTRL */
+			   <57 0 &mfx 10 0>;	/* DSI/TOUCH RESET */
+	};
+
 	aliases {
 		led0 = &green_led;
 		led1 = &orange_led;
@@ -345,3 +363,7 @@ st_cam_dvp: &dcmi {
 
 	pinctrl-names = "default";
 };
+
+/* alias used by display shields */
+zephyr_mipi_dsi: &mipi_dsi {};
+zephyr_lcd_controller: &ltdc {};

drivers/display/CMakeLists.txt

@@ -42,6 +42,7 @@ zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_GLCDC		display_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_ILI9806E_DSI		display_ili9806e_dsi.c)
 zephyr_library_sources_ifdef(CONFIG_ST7701 display_st7701.c)
 zephyr_library_sources_ifdef(CONFIG_LPM013M126 display_lpm013m126.c)
+zephyr_library_sources_ifdef(CONFIG_G1120TB101		display_g1120tb101.c)
 
 zephyr_library_sources_ifdef(CONFIG_MICROBIT_DISPLAY
 	mb_display.c

drivers/display/Kconfig

@@ -59,5 +59,6 @@ source "drivers/display/Kconfig.renesas_ra"
 source "drivers/display/Kconfig.ili9806e_dsi"
 source "drivers/display/Kconfig.st7701"
 source "drivers/display/Kconfig.lpm013m126"
+source "drivers/display/Kconfig.g1120tb101"
 
 endif # DISPLAY

drivers/display/Kconfig.g1120tb101

@@ -0,0 +1,20 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config G1120TB101
+	bool "G1120TB101 display controller"
+	default y
+	depends on DT_HAS_GVO_G1120TB101_ENABLED
+	select MIPI_DSI
+	help
+	  Enable the driver for GVO G1120TB101 display controller.
+
+if G1120TB101
+
+config DISPLAY_G1120TB101_INIT_PRIORITY
+	int "Initialization priority"
+	default DISPLAY_INIT_PRIORITY
+	help
+	  G1120TB101 display driver initialization priority.
+
+endif