drivers: flash: spi_nor: optimizations and better Micron flash support #88467
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Looks like the drivers.console.line_splitting.plus.some_option test is currently failing, for presumably unrelated reasons.. |
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Ping.. any feedback? |
de-nordic
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de-nordic
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Pull Request Overview
This pull request improves SPI NOR flash support by optimizing read operations and adding better support for Micron flash devices.
- Introduces new device tree properties for flag status register and fast read support.
- Adds corresponding flag and command definitions in the SPI NOR driver headers and source.
- Modifies the access and read functions to handle dummy bytes and leverage the flag status register when available.
Reviewed Changes
Copilot reviewed 3 out of 3 changed files in this pull request and generated 1 comment.
| File | Description |
|---|---|
| dts/bindings/mtd/jedec,spi-nor-common.yaml | Adds DT properties for flag status register and fast read. |
| drivers/flash/spi_nor.h | Introduces flag status register bits and new flash command macros. |
| drivers/flash/spi_nor.c | Updates access and read routines to support fast read and flag status register operations. |
Comments suppressed due to low confidence (1)
drivers/flash/spi_nor.c:471
- [nitpick] Consider consolidating the similar fast-read command macros to reduce code duplication and improve maintainability.
#define spi_nor_cmd_addr_fast_read(dev, opcode, addr, dest, length) \
| } else { | ||
| memcpy(&buf[1], &addr32.u8[1], 3); | ||
| spi_buf[0].len += 3; | ||
| spi_buf_tx[0].len += 3; | ||
| spi_buf_rx[0].len += 3; | ||
| } | ||
| }; |
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[nitpick] Consider adding a comment clarifying that the dummy byte is intentionally left with its default (zero) value to improve code clarity.
Suggested change
| }; | |
| }; | |
| /* If a dummy byte is required, increase the buffer lengths. | |
| * The dummy byte is intentionally left with its default (zero) value | |
| * as it serves as a placeholder for timing or protocol requirements. | |
| */ |
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de-nordic
previously approved these changes
May 8, 2025
anangl
reviewed
May 8, 2025
| @@ -496,8 +518,8 @@ static int spi_nor_wait_until_ready(const struct device *dev, k_timeout_t poll_d | |||
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| while (true) { | |||
| /* If flag status register is present, check it rather than the standard | |||
| * status register since it allows better error detection (and some devices | |||
| * that have it require it to be read after a program operation). | |||
| * status register since it allows better error detection. Also, some devices | |||
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This correction should be done in the second commit.
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Indeed, not sure how it ended up in the third one. Moved this change to the second commit.
drivers/flash/spi_nor.c
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| const struct spi_buf_set tx_set = { | ||
| .buffers = spi_buf, | ||
| .buffers = spi_buf_tx, | ||
| .count = (length != 0) ? 2 : 1, |
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You could just change this line to:
Suggested change
| .count = (length != 0) ? 2 : 1, | |
| .count = (is_write && length != 0) ? 2 : 1, |
to prevent that undesired use of data for TX in RX transactions.
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Yes, it looks like this works and simplifies things a bit.
This driver was providing SPI buffers for both TX and RX on the data payload portion of read transfers, even though the TX buffer is not meaningful in these cases. As well as being less efficient, this also caused likely uninitialized data to be transferred to the device, which is possibly problematic. Update to not include the TX buffer for the read data payload SPI transfer, so that the SPI driver can generate dummy TX data internally. Signed-off-by: Robert Hancock <[email protected]>
Some Micron (and possibly other) SPI NOR devices implement a flag status register which provides more information on the success/failure of erase and program operations. In addition to better error checking, some of these devices actually don't function properly if the flag status register is not read after a program operation (subsequent reads will only return 0xFF bytes). Add a device tree parameter to indicate that the flag status register is supported. When specified, the flag status register will be used for ready/error checks rather than the standard status register. Signed-off-by: Robert Hancock <[email protected]>
Most SPI NOR flash devices support a "fast read" command which uses dummy bits between the address and the start of the data transfer. In many cases, the maximum SPI clock speed of the device is lower for the regular read command due to the limited time between the address and data phases, so using the fast read command will remove this restriction and allow for faster transfers. Add a device tree flag to indicate that fast reads should be used for the device. Signed-off-by: Robert Hancock <[email protected]>
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anangl
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May 9, 2025
de-nordic
approved these changes
May 13, 2025
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Note, there might be a compliance error raised, as I wasn't able to satisfy both clang-format and checkpatch with regard to how one line was formatted..