drivers: spi: Added ZynqMP Generic Quad SPI driver

[robhancocksed]

Add a driver for the Generic Quad SPI hardware that is part of the Xilinx MPSoC. This is mostly commonly used with QSPI flash devices which are also used for initial image loading, but can also be used with other SPI devices.

Also added corresponding settings for the QSPI device and emulated flash devices for the QEMU Cortex-R5 board.

[robhancocksed]

Ping.. any feedback?

[robhancocksed]

Ping, needs review

[AmitMahapatra]

Hello @robhancocksed

I ran Ztest suite and sample tests for flash devices with the patch series. The tests passed on QEMU but are failing on the actual hardware.

regards,
Amit

[robhancocksed]

@AmitMahapatra , note that if you are testing on boards with certain Micron flash devices, such as ZCU102, you will need the patches from #88467 since those devices require the flag status register to be read after each program operation, otherwise they get into a state where all following reads return zeros. You will also need the appropriate flags in DT to enable that usage. These are the DT entries I have at the board level which are working for me on ZCU102 with those patches in place:

&qspi {
	status = "okay";
	clock-frequency = <124987511>;

	flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0>;
		spi-max-frequency = <166000000>;
		use-flag-status-register;
		use-fast-read;
	};

	flash@1 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x1>;
		spi-max-frequency = <166000000>;
		use-flag-status-register;
		use-fast-read;
	};
};

[tbursztyka]

you can skip dual and octal too, there is nothing in the SPI API to enable the proper use of dual/quad/octal. (there was a plan to do so years ago...)

[robhancocksed]

It does have support for basic dual/quad reads/writes which might be useful for some use cases. However, as you noted the SPI API would probably need more fine-grained control to be usable for QSPI flash in those modes, for example..

[robhancocksed]

Rebased to main, and added a fix for the shared-data-bus DT parameter not taking effect properly.

[kartben]

POL and PH swapped?

[robhancocksed]

Indeed, fixed now.

[Copilot]

Pull Request Overview

This PR adds a new Generic Quad SPI (GQSPI) driver for the Xilinx ZynqMP platform along with the necessary device tree bindings and configuration updates for both hardware and emulated environments.

• Added a dts binding file for the ZynqMP QSPI interface.
• Updated device tree source (DTS) files to integrate the new QSPI node configurations for both ARM and QEMU boards.
• Added Kconfig and CMakeLists entries to enable building the new driver.

Reviewed Changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated no comments.

Show a summary per file

File	Description
dts/bindings/spi/xlnx,zynqmp-qspi-1.0.yaml	New binding file defining properties for the ZynqMP QSPI driver.
dts/arm/xilinx/zynqmp.dtsi	Added QSPI node configuration for integration with the DT.
drivers/spi/Kconfig.xlnx_zynqmp_gqspi	New Kconfig file for enabling the ZynqMP GQSPI driver.
drivers/spi/Kconfig	Updated to source the new Kconfig file.
drivers/spi/CMakeLists.txt	Added driver source file for the ZynqMP GQSPI driver.
boards/qemu/cortex_r5/qemu_cortex_r5.dts	Enabled QSPI and updated flash definitions for the QEMU board.
boards/qemu/cortex_r5/Kconfig.defconfig	Added default configuration for SPI NOR SFDP selection.

[sonarqubecloud]

Quality Gate passed

Issues
1 New issue
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud