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db
db
 
 
incremental_db
incremental_db
 
 
output_files
output_files
 
 
CPU.qsf
CPU.qsf
 
 
CPU.qws
CPU.qws
 
 
CPU_nativelink_simulation.rpt
CPU_nativelink_simulation.rpt
 
 
MDMux.v
MDMux.v
 
 
MDMux.v.bak
MDMux.v.bak
 
 
MDR.v
MDR.v
 
 
MDR.v.bak
MDR.v.bak
 
 
MDR_unit.v
MDR_unit.v
 
 
MDR_unit.v.bak
MDR_unit.v.bak
 
 
PC_reg.v
PC_reg.v
 
 
PC_reg.v.bak
PC_reg.v.bak
 
 
README.md
README.md
 
 
add_new.v
add_new.v
 
 
add_new.v.bak
add_new.v.bak
 
 
add_new_tb.v
add_new_tb.v
 
 
add_new_tb.v.bak
add_new_tb.v.bak
 
 
alu.v
alu.v
 
 
alu.v.bak
alu.v.bak
 
 
alu_tb.v
alu_tb.v
 
 
alu_tb.v.bak
alu_tb.v.bak
 
 
and_new.v
and_new.v
 
 
and_new.v.bak
and_new.v.bak
 
 
and_new_tb.v
and_new_tb.v
 
 
and_new_tb.v.bak
and_new_tb.v.bak
 
 
bidirectionalBus.v
bidirectionalBus.v
 
 
bidirectionalBus.v.bak
bidirectionalBus.v.bak
 
 
binary_shift_left.v
binary_shift_left.v
 
 
binary_shift_right.v
binary_shift_right.v
 
 
bus.v
bus.v
 
 
bus.v.bak
bus.v.bak
 
 
busMux.v
busMux.v
 
 
busMux.v.bak
busMux.v.bak
 
 
dataPath.v
dataPath.v
 
 
dataPath.v.bak
dataPath.v.bak
 
 
dataPath_tb.v
dataPath_tb.v
 
 
dataPath_tb.v.bak
dataPath_tb.v.bak
 
 
datapath_new.v
datapath_new.v
 
 
datapath_new.v.bak
datapath_new.v.bak
 
 
datapath_new_tb.v
datapath_new_tb.v
 
 
datapath_new_tb.v.bak
datapath_new_tb.v.bak
 
 
div_new.v
div_new.v
 
 
div_new.v.bak
div_new.v.bak
 
 
div_new_tb.v
div_new_tb.v
 
 
div_new_tb.v.bak
div_new_tb.v.bak
 
 
encoder.v
encoder.v
 
 
encoder.v.bak
encoder.v.bak
 
 
encoder_tb.v
encoder_tb.v
 
 
encoder_tb.v.bak
encoder_tb.v.bak
 
 
fulladder_new.v
fulladder_new.v
 
 
fulladder_new.v.bak
fulladder_new.v.bak
 
 
fulladder_new_tb.v
fulladder_new_tb.v
 
 
fulladder_new_tb.v.bak
fulladder_new_tb.v.bak
 
 
mul_new.txt
mul_new.txt
 
 
mul_new.v
mul_new.v
 
 
mul_new.v.bak
mul_new.v.bak
 
 
mul_new_tb.v
mul_new_tb.v
 
 
mul_new_tb.v.bak
mul_new_tb.v.bak
 
 
myCPU.qpf
myCPU.qpf
 
 
neg_new.v
neg_new.v
 
 
neg_new.v.bak
neg_new.v.bak
 
 
neg_new_tb.v
neg_new_tb.v
 
 
neg_new_tb.v.bak
neg_new_tb.v.bak
 
 
not_new.v
not_new.v
 
 
not_new.v.bak
not_new.v.bak
 
 
not_new_tb.v
not_new_tb.v
 
 
not_new_tb.v.bak
not_new_tb.v.bak
 
 
or_new.v
or_new.v
 
 
or_new.v.bak
or_new.v.bak
 
 
or_new_tb.v
or_new_tb.v
 
 
or_new_tb.v.bak
or_new_tb.v.bak
 
 
register.v
register.v
 
 
register.v.bak
register.v.bak
 
 
register_64_bits.v
register_64_bits.v
 
 
register_64_bits.v.bak
register_64_bits.v.bak
 
 
register_tb.v
register_tb.v
 
 
register_tb.v.bak
register_tb.v.bak
 
 
rotate_left.v
rotate_left.v
 
 
rotate_left.v.bak
rotate_left.v.bak
 
 
rotate_right.v
rotate_right.v
 
 
rotate_right.v.bak
rotate_right.v.bak
 
 
shift_right_arithmetic.v
shift_right_arithmetic.v
 
 
shift_right_arithmetic.v.bak
shift_right_arithmetic.v.bak
 
 
shift_right_arithmetic_tb.v
shift_right_arithmetic_tb.v
 
 
shift_right_arithmetic_tb.v.bak
shift_right_arithmetic_tb.v.bak
 
 
sub_new.v
sub_new.v
 
 
sub_new.v.bak
sub_new.v.bak
 
 
sub_new_tb.v
sub_new_tb.v
 
 
sub_new_tb.v.bak
sub_new_tb.v.bak
 
 

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CPU-Design

Designed a CPU using Verilog

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Designed a CPU using Verilog

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